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CY7C135-35JCR PDF预览

CY7C135-35JCR

更新时间： 2024-11-26 13:00:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
12页 402K
描述
Dual-Port SRAM, 4KX8, 35ns, CMOS, PQCC52, PLASTIC, LCC-52

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中文翻译

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CY7C135-35JCR 技术参数

生命周期：Obsolete零件包装代码：LCC
包装说明：QCCJ,针数：52
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.53
Is Samacsys：N最长访问时间：35 ns
JESD-30 代码：S-PQCC-J52长度：19.1262 mm
内存密度：32768 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：8功能数量：1
端口数量：2端子数量：52
字数：4096 words字数代码：4000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：4KX8
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：5.08 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：19.1262 mmBase Number Matches：1

CY7C135-35JCR 数据手册

 浏览型号CY7C135-35JCR的Datasheet PDF文件第2页浏览型号CY7C135-35JCR的Datasheet PDF文件第3页浏览型号CY7C135-35JCR的Datasheet PDF文件第4页浏览型号CY7C135-35JCR的Datasheet PDF文件第5页浏览型号CY7C135-35JCR的Datasheet PDF文件第6页浏览型号CY7C135-35JCR的Datasheet PDF文件第7页 
CY7C135  
CY7C1342  
4K x 8 Dual-Port Static RAM and 4K x 8  
Dual-Port SRAM with Semaphores  
Functional Description  
Features  
• True Dual-Ported memory cells which allow simulta-  
neous reads of the same memory location  
The CY7C135 and CY7C1342 are high-speed CMOS 4K x 8  
dual-port static RAMs. The CY7C1342 includes semaphores  
that provide a means to allocate portions of the dual-port RAM  
or any shared resource. Two ports are provided permitting  
independent, asynchronous access for reads and writes to  
any location in memory. Application areas include interpro-  
cessor/multiprocessor designs, communications status  
buffering, and dual-port video/graphics memory.  
• 4K x 8 organization  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 15 ns  
• Low operating power: ICC = 160 mA (max.)  
• Fully asynchronous operation  
• Automatic power-down  
Each port has independent control pins: chip enable (CE),  
read or write enable (R/W), and output enable (OE). The  
CY7C135 is suited for those systems that do not require  
on-chip arbitration or are intolerant of wait states. Therefore,  
the user must be aware that simultaneous access to a location  
is possible. Semaphores are offered on the CY7C1342 to  
assist in arbitrating between ports. The semaphore logic is  
comprised of eight shared latches. Only one side can control  
the latch (semaphore) at any time. Control of a semaphore  
indicates that a shared resource is in use. An automatic  
power-down feature is controlled independently on each port  
by a chip enable (CE) pin or SEM pin (CY7C1342 only).  
• Semaphoresincludedonthe7C1342topermitsoftware  
handshaking between ports  
• Available in 52-pin PLCC  
• Pb-Free packages available  
The CY7C135 and CY7C1342 are available in 52-pin PLCC.  
Logic Block Diagram  
R/W  
L
R/W  
R
CE  
OE  
CE  
R
L
OE  
R
L
I/O  
I/O  
7L  
7R  
0R  
I/O  
CONTROL  
I/O  
CONTROL  
I/O  
0L  
I/O  
A
A
11L  
0L  
11R  
0R  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
MEMORY  
ARRAY  
A
A
SEMAPHORE  
ARBITRATION  
(7C1342 only)  
CE  
L
CE  
R
OE  
L
OE  
R
R/W  
R/W  
R
L
(7C1342 only)  
(7C1342 only)  
SEM  
SEM  
R
L
Cypress Semiconductor Corporation  
Document #: 38-06038 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 6, 2005  
1234567...12

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CY7C135-35JCT CYPRESS

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CY7C135-35JI CYPRESS

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 		4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
CY7C135-35JIR CYPRESS

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CY7C135-35JIT CYPRESS

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 		Dual-Port SRAM, 4KX8, 35ns, CMOS, PQCC52, PLASTIC, LCC-52
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CY7C1353-66ACT CYPRESS

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CY7C1353B CYPRESS

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 		256Kx18 Flow-Through SRAM with NoBL Architecture
CY7C1353B-100AC CYPRESS

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 		256Kx18 Flow-Through SRAM with NoBL Architecture
CY7C1353B-100ACT CYPRESS

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 		ZBT SRAM, 256KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1353B-117AC CYPRESS

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 		256Kx18 Flow-Through SRAM with NoBL Architecture

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