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CY7C135-35JC PDF预览

CY7C135-35JC

更新时间： 2024-11-25 22:02:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
12页 554K
描述
4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores

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中文翻译

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CY7C135-35JC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：LCC包装说明：PLASTIC, LCC-52
针数：52Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.84最长访问时间：35 ns
I/O 类型：COMMONJESD-30 代码：S-PQCC-J52
JESD-609代码：e0长度：19.1262 mm
内存密度：32768 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：8功能数量：1
端口数量：2端子数量：52
字数：4096 words字数代码：4000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：4KX8
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC52,.8SQ封装形状：SQUARE
封装形式：CHIP CARRIER并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：5.08 mm
最大待机电流：0.015 A最小待机电流：4.5 V
子类别：SRAMs最大压摆率：0.16 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：19.1262 mm
Base Number Matches：1

CY7C135-35JC 数据手册

 浏览型号CY7C135-35JC的Datasheet PDF文件第2页浏览型号CY7C135-35JC的Datasheet PDF文件第3页浏览型号CY7C135-35JC的Datasheet PDF文件第4页浏览型号CY7C135-35JC的Datasheet PDF文件第5页浏览型号CY7C135-35JC的Datasheet PDF文件第6页浏览型号CY7C135-35JC的Datasheet PDF文件第7页 
CY7C135  
CY7C1342  
4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port  
SRAM with Semaphores  
Features  
Functional Description  
• True Dual-Ported memory cells which allow simulta-  
The CY7C135 and CY7C1342 are high-speed CMOS 4K x 8  
dual-port static RAMs. The CY7C1342 includes semaphores  
that provide a means to allocate portions of the dual-port RAM  
or any shared resource. Two ports are provided permitting in-  
dependent, asynchronous access for reads and writes to any  
location in memory. Application areas include interproces-  
sor/multiprocessor designs, communications status buffering,  
and dual-port video/graphics memory.  
neous reads of the same memory location  
• 4K x 8 organization  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 15 ns  
• Low operating power: ICC = 160 mA (max.)  
• Fully asynchronous operation  
• Automatic power-down  
• Semaphoresincludedonthe7C1342topermitsoftware  
handshaking between ports  
• Available in 52-pin PLCC  
Each port has independent control pins: chip enable (CE),  
read or write enable (R/W), and output enable (OE). The  
CY7C135 is suited for those systems that do not require  
on-chip arbitration or are intolerant of wait states. Therefore,  
the user must be aware that simultaneous access to a location  
is possible. Semaphores are offered on the CY7C1342 to as-  
sist in arbitrating between ports. The semaphore logic is com-  
prised of eight shared latches. Only one side can control the  
latch (semaphore) at any time. Control of a semaphore indi-  
cates that a shared resource is in use. An automatic pow-  
er-down feature is controlled independently on each port by a  
chip enable (CE) pin or SEM pin (CY7C1342 only).  
The CY7C135 and CY7C1342 are available in 52-pin PLCC.  
Logic Block Diagram  
R/W  
L
R/W  
R
CE  
L
CE  
R
OE  
R
OE  
L
I/O  
7L  
I/O  
I/O  
7R  
I/O  
CONTROL  
I/O  
CONTROL  
I/O  
0L  
0R  
A
A
11L  
0L  
11R  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
MEMORY  
ARRAY  
A
A
0R  
SEMAPHORE  
ARBITRATION  
(7C1342 only)  
CE  
L
CE  
R
OE  
L
OE  
R
R/W  
R/W  
R
L
(7C1342 only)  
(7C1342 only)  
1342–1  
SEM  
R
SEM  
L
Cypress Semiconductor Corporation  
Document #: 38-06038 Rev. *B  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised June 22, 2004  
1234567...12

中文翻译

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与CY7C135-35JC相关器件

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CY7C135-35JCR CYPRESS

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 		Dual-Port SRAM, 4KX8, 35ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C135-35JCT CYPRESS

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 		Dual-Port SRAM, 4KX8, 35ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C135-35JI CYPRESS

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 		4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
CY7C135-35JIR CYPRESS

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 		Dual-Port SRAM, 4KX8, 35ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C135-35JIT CYPRESS

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 		Dual-Port SRAM, 4KX8, 35ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C1353-66AC CYPRESS

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 		256Kx18 Flow-Through SRAM with NoBL Architecture
CY7C1353-66ACT CYPRESS

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 		暂无描述
CY7C1353B CYPRESS

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 		256Kx18 Flow-Through SRAM with NoBL Architecture
CY7C1353B-100AC CYPRESS

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 		256Kx18 Flow-Through SRAM with NoBL Architecture
CY7C1353B-100ACT CYPRESS

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 		ZBT SRAM, 256KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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