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CY7C1352G-166AXI PDF预览

CY7C1352G-166AXI

更新时间： 2024-11-25 22:17:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 内存集成电路静态存储器
页数 文件大小 规格书
13页 224K
描述
4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture

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CY7C1352G-166AXI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100
针数：100Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.75最长访问时间：3.5 ns
其他特性：PIPELINED ARCHITECTUREI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e3
长度：20 mm内存密度：4718592 bit
内存集成电路类型：ZBT SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：100字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.04 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.24 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：14 mm
Base Number Matches：1

CY7C1352G-166AXI 数据手册

 浏览型号CY7C1352G-166AXI的Datasheet PDF文件第2页浏览型号CY7C1352G-166AXI的Datasheet PDF文件第3页浏览型号CY7C1352G-166AXI的Datasheet PDF文件第4页浏览型号CY7C1352G-166AXI的Datasheet PDF文件第5页浏览型号CY7C1352G-166AXI的Datasheet PDF文件第6页浏览型号CY7C1352G-166AXI的Datasheet PDF文件第7页 
CY7C1352G  
PRELIMINARY  
4-Mbit (256Kx18) Pipelined SRAM  
with NoBL™ Architecture  
Features  
Functional Description[1]  
• Pin compatible and functionally equivalent to ZBT™  
devices  
The CY7C1352G is a 3.3V, 256K x 18 synchronous-pipelined  
Burst SRAM designed specifically to support unlimited true  
back-to-back Read/Write operations without the insertion of  
wait states. The CY7C1352G is equipped with the advanced  
No Bus Latency™ (NoBL™) logic required to enable consec-  
utive Read/Write operations with data being transferred on  
every clock cycle. This feature dramatically improves the  
throughput of the SRAM, especially in systems that require  
frequent Write/Read transitions.  
• Internally self-timed output buffer control to eliminate  
the need to use OE  
• Byte Write capability  
• 256K x 18 common I/O architecture  
• Single 3.3V power supply  
• 2.5V / 3.3V I/O Operation  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which, when deasserted, suspends operation and extends the  
previous clock cycle. Maximum access delay from the clock  
rise is 2.6 ns (250-MHz device).  
• Fast clock-to-output times  
• 2.6 ns (for 250-MHz device)  
• 2.8 ns (for 200-MHz device)  
• 3.5 ns (for 166-MHz device)  
• 4.0 ns (for 133-MHz device)  
Write operations are controlled by the two Byte Write Select  
(BW[A:B]) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
• Asynchronous output enable (OE)  
• Pb-Free 100 TQFP package  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
• Burst Capability—linear or interleaved burst order  
• ZZ” Sleep Mode Option and Stop Clock option  
Logic Block Diagram  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
Q1  
A0'  
Q0  
D1  
D0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD  
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
A
R
E
G
I
S
T
E
R
S
MEMORY  
ARRAY  
E
B
U
F
DQs  
DQP  
DQP  
WRITE  
DRIVERS  
BW  
A
B
S
T
E
E
R
I
A
M
P
A
B
F
BW  
E
R
S
S
N
G
WE  
E
E
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
Sleep  
Control  
ZZ  
Notes:  
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05514 Rev. *A  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised November 10, 2004  
1234567...13

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与CY7C1352G-166AXI相关器件

型号 品牌 获取价格 描述 数据表
CY7C1352G-166AXIT CYPRESS

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 		ZBT SRAM, 256KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1352G-200AXC CYPRESS

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 		4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture
CY7C1352G-200AXI CYPRESS

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 		4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture
CY7C1352G-250AXC CYPRESS

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 		4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture
CY7C1352G-250AXCT CYPRESS

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 		ZBT SRAM, 256KX18, 2.6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQ
CY7C1352G-250AXI CYPRESS

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 		4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture
CY7C1353 CYPRESS

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 		256Kx18 Flow-Through SRAM with NoBL Architecture
CY7C1353-40AC CYPRESS

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 		256Kx18 Flow-Through SRAM with NoBL Architecture
CY7C1353-40ACT CYPRESS

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 		ZBT SRAM, 256KX18, 14ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1353-50AC CYPRESS

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 		256Kx18 Flow-Through SRAM with NoBL Architecture

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