CY7C1352F-225AI

更新时间： 2024-11-25 22:17:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
13页	292K
描述
4-Mbit (256Kx18) Pipelined SRAM with NoBL⑩ Architecture

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CY7C1352F-225AI 数据手册

CY7C1352F

4-Mbit (256Kx18) Pipelined SRAM

with NoBL™ Architecture

Functional Description^[1]

Features

• Pin compatible and functionally equivalent to ZBT™

The CY7C1352F is a 3.3V, 256K x 18 synchronous-pipelined

Burst SRAM designed specifically to support unlimited true

back-to-back Read/Write operations without the insertion of

wait states. The CY7C1352F is equipped with the advanced

No Bus Latency™ (NoBL™) logic required to enable consec-

utive Read/Write operations with data being transferred on

every clock cycle. This feature dramatically improves the

throughput of the SRAM, especially in systems that require

frequent Write/Read transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which, when deasserted, suspends operation and extends the

previous clock cycle. Maximum access delay from the clock

rise is 2.8 ns (200-MHz device)

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Byte Write capability

• 256K x 18 common I/O architecture

• Single 3.3V power supply

• 2.5V / 3.3V I/O Operation

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.6 ns (for 225-MHz device)

— 2.8 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 100-MHz device)

Write operations are controlled by the two Byte Write Select

(BW_[A:B]) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous output enable (OE)

• JEDEC-standard 100 TQFP package

• Burst Capability—linear or interleaved burst order

• “ZZ” Sleep Mode Option and Stop Clock option

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Logic Block Diagram

A0, A1, A

ADDRESS

A1'

A0'

BURST

LOGIC

MODE

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

MEMORY

ARRAY

DQs

DQP

WRITE

DRIVERS

INPUT

READ LOGIC

CE1

CE2

CE3

Sleep

Control

Note:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05211 Rev. *C

Revised April 16, 2004

12 3 4 5 6 7...13

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与CY7C1352F-225AI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1352F-250AC	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL⑩ Ar
CY7C1352F-250AI	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL⑩ Ar
CY7C1352G	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture
CY7C1352G_06	CYPRESS	获取价格	4-Mbit (256K x 18) Pipelined SRAM with NoBL⑩
CY7C1352G_12	CYPRESS	获取价格	4-Mbit (256 K Ã 18) Pipelined SRAM with NoBL
CY7C1352G_13	CYPRESS	获取价格	4-Mbit (256 K x 18) Pipelined SRAM with NoBLâ
CY7C1352G-133AXC	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture
CY7C1352G-133AXC	INFINEON	获取价格	Synchronous SRAM
CY7C1352G-133AXI	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture
CY7C1352G-166AXC	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture

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