Datasheet > 存储 > SRAM> CY7C1352B-143AC

CY7C1352B-143AC

更新时间： 2024-11-05 22:45:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
12页	190K
描述
256K x 18 Pipilined SRAm with NoBL Architecture

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技术参数
数据手册

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CY7C1352B-143AC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：	100	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.83	Is Samacsys：	N
最长访问时间：	4 ns	最大时钟频率 (fCLK)：	143 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0	长度：	20 mm
内存密度：	4718592 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	18	功能数量：	1
端子数量：	100	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.005 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.35 mA
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

CY7C1352B-143AC 数据手册

PRELIMINARY

CY7C1352B

256K x18 Pipelined SRAM with NoBL™ Architecture

• Low standby power

Features

Functional Description

• Pin compatible and functionally equivalent to ZBT™

devices MCM63Z818 and MT55L256L18P

The CY7C1352B is a 3.3V 256K by 18 synchronous-pipelined

Burst SRAM designed specifically to support unlimited true

back-to-back Read/Write operations without the insertion of

wait states. The CY7C1352B is equipped with the advanced

No Bus Latency™ (NoBL™) logic required to enable consec-

utive Read/Write operations with data being transferred on ev-

ery clock cycle. This feature dramatically improves the

throughput of the SRAM, especially in systems that require

frequent Read/Write transitions. The CY7C1352B is pin/func-

tionally compatible to ZBT SRAMs MCM63Z819 and

MT55L256L18P.

• Supports 166-MHz bus operations with zero wait states

— Data is transferred on every clock

• Internally self-timed output buffer control to eliminate

the need to use OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write Capability

• 256K x 18 common I/O architecture

• Single 3.3V power supply

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal, which

when deasserted suspends operation and extends the previ-

ous clock cycle. Maximum access delay from the clock rise is

3.5 ns (166-MHz device).

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

— 3.8 ns (for 150-MHz device)

— 4.0 ns (for 143-MHz device)

— 4.2 ns (for 133-MHz device)

— 5.0 ns (for 100-MHz device)

Write operations are controlled by the four Byte Write Select

— 7.0 ns (for 80-MHz device)

(BWS

) and a Write Enable (WE) input. All writes are con-

[1:0]

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous output enable

• JEDEC-standard 100-pin TQFP package

• Burst Capability—linear or interleaved burst order

ducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE , CE , CE ) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

A_[17:0]

CEN

CONTROL

and WRITE

LOGIC

256Kx18

MEMORY

DQ_[15:0]

DP_[1:0]

ARRAY

BWS

[1:0]

Mode

Selection Guide

-166

3.5

400

-150

3.8

375

-143

4.0

350

-133

4.2

300

-100

5.0

250

-80

7.0

200

Maximum Access Time (ns)

Maximum Operating Current (mA)

Commercial

Maximum CMOS Standby Current (mA) Commercial

Shaded areas contain advance information.

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.

ZBT is a trademark of Integrated Device Technology.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

May 26, 2000

12 3 4 5 6 7...12

中文翻译

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与CY7C1352B-143AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1352B-143ACT	CYPRESS	获取价格	ZBT SRAM, 256KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1352B-150AC	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1352B-166AC	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1352B-80AC	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1352F	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL⑩ Ar
CY7C1352F-100AC	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL⑩ Ar
CY7C1352F-100AI	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL⑩ Ar
CY7C1352F-133AC	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL⑩ Ar
CY7C1352F-133AI	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL⑩ Ar
CY7C1352F-166AC	CYPRESS	获取价格	4-Mbit (256Kx18) Pipelined SRAM with NoBL⑩ Ar

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