Datasheet > CY7C1352-133AI

CY7C1352-133AI

更新时间： 2024-11-25 23:45:27

品牌	Logo	应用领域
其他 - ETC		内存集成电路静态存储器时钟
页数	文件大小	规格书
13页	310K
描述
x18 Fast Synchronous SRAM

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CY7C1352-133AI 数据手册

1CY7C1352

CY7C1352

256K x18 Pipelined SRAM with NoBL™ Architecture

• Low standby power

Features

Functional Description

• Pin compatible and functionally equivalent to ZBT™

devices MCM63Z818 and MT55L256L18P

The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined

Burst SRAM designed specifically to support unlimited true

back-to-back Read/Write operations without the insertion of

wait states. The CY7C1352 is equipped with the advanced No

Bus Latency™ (NoBL™) logic required to enable consecutive

Read/Write operations with data being transferred on every

clock cycle. This feature dramatically improves the throughput

of the SRAM, especially in systems that require frequent

Read/Write transitions.The CY7C1352 is pin/functionally com-

patible to ZBT™ SRAMs MCM63Z819 and MT55L256L18P.

• Supports 143-MHz bus operations with zero wait states

— Data is transferred on every clock

• Internally self-timed output buffer control to eliminate

the need to use OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write Capability

• 256K x 18 common I/O architecture

• Single 3.3V power supply

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal, which

when deasserted suspends operation and extends the previ-

ous clock cycle. Maximum access delay from the clock rise is

4.0 ns (143-MHz device).

• Fast clock-to-output times

— 4.0 ns (for 143-MHz device)

— 4.2 ns (for 133-MHz device)

— 5.0 ns (for 100-MHz device)

Write operations are controlled by the four Byte Write Select

(BWS_[1:0]) and a Write Enable (WE) input. All writes are con-

ducted with on-chip synchronous self-timed write circuitry.

— 7.0 ns (for 80-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous output enable

• JEDEC-standard 100-pin TQFP package

• Burst Capability—linear or interleaved burst order

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

[17:0]

CEN

CONTROL

and WRITE

LOGIC

256Kx18

MEMORY

[15:0]

[1:0]

ARRAY

[1:0]

BWS

Mode

Selection Guide

7C1352-143

7C1352-133

7C1352-100

7C1352-80

Maximum Access Time (ns)

4.0

450

4.2

400

5.0

350

7.0

300

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Commercial

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.

ZBT is a trademark of Integrated Device Technology.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

March 14, 2001

12 3 4 5 6 7...13

中文翻译

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与CY7C1352-133AI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1352-143AC	CYPRESS	获取价格	256K x18 Pipelined SRAM with NoBL Architecture
CY7C135-25JC	CYPRESS	获取价格	4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
CY7C135-25JCT	CYPRESS	获取价格	Dual-Port SRAM, 4KX8, 25ns, CMOS, PQCC52, PLASTIC, LCC-52
CY7C135-25JI	CYPRESS	获取价格	4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
CY7C135-25JXC	CYPRESS	获取价格	4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
CY7C1352-80AC	CYPRESS	获取价格	256K x18 Pipelined SRAM with NoBL Architecture
CY7C1352B	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1352B-100AC	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture
CY7C1352B-100ACT	CYPRESS	获取价格	暂无描述
CY7C1352B-133AC	CYPRESS	获取价格	256K x 18 Pipilined SRAm with NoBL Architecture

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