5秒后页面跳转
捷配首页

Datasheet > CY62168G18-55BVXIT
CY62168G18-55BVXIT PDF预览

CY62168G18-55BVXIT

更新时间： 2024-11-06 01:02:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
19页 312K
描述
16-Mbit (2M words × 8 bits) Static RAM with Error-Correcting Code (ECC)

阅读下载

中文翻译

获取价格

CY62168G18-55BVXIT 数据手册

 浏览型号CY62168G18-55BVXIT的Datasheet PDF文件第2页浏览型号CY62168G18-55BVXIT的Datasheet PDF文件第3页浏览型号CY62168G18-55BVXIT的Datasheet PDF文件第4页浏览型号CY62168G18-55BVXIT的Datasheet PDF文件第5页浏览型号CY62168G18-55BVXIT的Datasheet PDF文件第6页浏览型号CY62168G18-55BVXIT的Datasheet PDF文件第7页 
CY62168G/CY62168GE MoBL®  
16-Mbit (2M words × 8 bits) Static RAM  
with Error-Correcting Code (ECC)  
16-Mbit (2M words  
× 8 bits) Static RAM with Error-Correcting Code (ECC)  
Devices with a single chip enable input are accessed by  
asserting the chip enable input (CE) LOW. Dual chip enable  
devices are accessed by asserting both chip enable inputs – CE1  
as LOW and CE2 as HIGH.  
Features  
■ Ultra-low standby power  
❐ Typical standby current: 5.5 A  
❐ Maximum standby current: 16 A  
Write to the device by taking Chip Enable 1 (CE1) LOW and  
Chip Enable 2 (CE2) HIGH and the Write Enable (WE) input  
LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written  
■ High speed: 45 ns/55 ns  
into the location specified on the address pins (A0 through A20).  
■ Embedded error-correcting code (ECC) for single-bit error  
correction  
Read from the device by taking Chip Enable 1 (CE1) and  
Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while  
forcing Write Enable (WE) HIGH. Under these conditions, the  
contents of the memory location specified by the address pins  
will appear on the I/O pins.  
■ Widevoltage range: 1.65 V to2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V  
■ 1.0 V data retention  
■ Transistor-transistor logic (TTL) compatible inputs and outputs  
■ ERR pin to indicate 1-bit error detection and correction  
■ Available in Pb-free 48-ball VFBGA package  
The eight input and output pins (I/O0 through I/O7) are placed in  
a high impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a  
write operation is in progress (CE1 LOW and CE2 HIGH and WE  
LOW). See the Truth Table – CY62168G/CY62168GE on page  
14 for a complete description of read and write modes.  
Functional Description  
CY62168G and CY62168GE are high-performance CMOS  
low-power (MoBL) SRAM devices with embedded ECC. Both  
devices are offered in single and dual chip enable options and in  
multiple pin configurations. The CY62168GE device includes an  
error indication pin that signals a single-bit error-detection and  
correction event during a read cycle.  
On CY62168GE devices, the detection and correction of a single  
bit error in the accessed location is indicated by the assertion of  
the ERR output (ERR = HIGH) [1]  
.
The CY62168G and CY62168GE devices are available in a  
Pb-free 48-pin VFBGA package. The logic block diagrams are  
on page 2.  
For a complete list of related resources, click here.  
Product Portfolio  
Power Dissipation  
Features and Options  
(see Pin  
Operating ICC, (mA)  
Speed  
Product  
Range  
VCC Range (V)  
Standby, ISB2 (µA)  
(ns)  
Configurations  
section)  
f = fmax  
Typ[2]  
Max  
32  
Typ[2]  
7
Max  
26  
CY62168G(E)18 Single or dual Chip  
Industrial  
1.65 V–2.2 V  
2.2 V–3.6 V  
4.5 V–5.5 V  
55  
45  
29  
29  
Enables  
CY62168G(E)30  
36  
5.5  
16  
Optional ERR pin  
CY62168G(E)  
Notes  
1. This device does not support automatic write-back on error detection.  
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for V range of 1.65 V–2.2 V), V = 3 V  
CC  
CC  
CC  
(for V range of 2.2 V–3.6 V), and V = 5 V (for V range of 4.5 V–5.5 V), T = 25 °C.  
CC  
CC  
CC  
A
Cypress Semiconductor Corporation  
Document Number: 001-84771 Rev. *I  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised December 22, 2017  
1234567...19

中文翻译

下载PDF

与CY62168G18-55BVXIT相关器件

型号 品牌 获取价格 描述 数据表
CY62168G30-45BVXI CYPRESS

获取价格

 		16-Mbit (2M words × 8 bits) Static RAM with
CY62168G30-45BVXI INFINEON

获取价格

 		Asynchronous SRAM
CY62168G30-45BVXIT CYPRESS

获取价格

 		16-Mbit (2M words × 8 bits) Static RAM with
CY62168G30-45BVXIT INFINEON

获取价格

 		Asynchronous SRAM
CY62168GE CYPRESS

获取价格

 		16-Mbit (2M words × 8 bits) Static RAM with
CY62168GE30-45BVXI CYPRESS

获取价格

 		Standard SRAM, 2MX8, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62168GE30-45BVXI INFINEON

获取价格

 		Asynchronous SRAM
CY62168GE30-45BVXIT CYPRESS

获取价格

 		16-Mbit (2M words × 8 bits) Static RAM with
CY62168GE30-45BVXIT INFINEON

获取价格

 		Asynchronous SRAM
CY62168GN30-45BVXI INFINEON

获取价格

 		Asynchronous SRAM

与CY62168G18-55BVXIT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证