Datasheet > CY62177DV30_11

CY62177DV30_11

更新时间： 2024-11-05 09:42:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
14页	485K
描述
32-Mbit (2M x 16) Static RAM

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CY62177DV30_11 数据手册

CY62177DV30 MoBL^®

32-Mbit (2M x 16) Static RAM

applications such as cellular telephones.The device also has an

automatic power-down feature that significantly reduces power

consumption. The device can also be put into standby mode

when deselected (CE₁HIGH or CE₂LOW or both BHE and BLE

are HIGH). The input/output pins (I/O₀through I/O₁₅) are placed

in a high-impedance state when: deselected (CE₁HIGH or CE₂

LOW), outputs are disabled (OE HIGH), both Byte High Enable

and Byte Low Enable are disabled (BHE, BLE HIGH), or during

a write operation (CE₁LOW, CE₂HIGH and WE LOW).

Features

■ Very high speed: 55 ns

■ Wide voltage range: 2.20 V–3.60 V

■ Ultra-low active power

❐ Typical active current: 2 mA @ f = 1 MHz

❐ Typical active current: 15 mA @ f = f_max

■ Ultra low standby power

Writing to the device is accomplished by taking Chip Enables

(CE₁LOW and CE₂HIGH) and Write Enable (WE) input LOW. If

Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O₀

through I/O₇), is written into the location specified on the address

pins (A₀through A₂₀). If Byte High Enable (BHE) is LOW, then

data from I/O pins (I/O₈through I/O₁₅) is written into the location

specified on the address pins (A₀through A₂₀).

■ Easy memory expansion with CE₁, CE₂and OE features

■ Automatic power-down when deselected

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed/power

■ Packages offered in a 48-ball fine ball grid array (FBGA)

Reading from the device is accomplished by taking Chip Enables

(CE₁LOW and CE₂HIGH) and Output Enable (OE) LOW while

forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)

is LOW, then data from the memory location specified by the

address pins will appear on I/O₀to I/O₇. If Byte High Enable

(BHE) is LOW, then data from memory will appear on I/O₈to

I/O₁₅. See the truth table for a complete description of read and

write modes.

Functional Description^[1]

The CY62177DV30 is a high-performance CMOS static RAM

organized as 2M words by 16 bits. This device features

advanced circuit design to provide ultra-low active current. This

is ideal for providing More Battery Life (MoBL^®) in portable

Logic Block Diagram

DATA-IN DRIVERS

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

A ₄

A ₃

2048K × 16

RAM Array

I/O₀–I/O₇

I/O₈–I/O₁₅

A ₂

A ₁

A ₀

COLUMN DECODER

BHE

CE₂

BLE

Power-down

Circuit

Note

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document Number : 38-05633 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 25, 2011

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与CY62177DV30_11相关器件

型号	品牌	获取价格	描述	数据表
CY62177DV30_12	CYPRESS	获取价格	32-Mbit (2 M Ã 16) Static RAM
CY62177DV30L-55BAI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177DV30L-70BAI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177DV30LL	CYPRESS	获取价格	32-Mbit (2M x 16) Static RAM
CY62177DV30LL-55BAI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177DV30LL-55BAXI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177ESL-55ZXI	CYPRESS	获取价格	Standard SRAM, 2MX16, 55ns, CMOS, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, LEAD FREE, MO-142, T
CY62177ESL-55ZXIT	CYPRESS	获取价格	Standard SRAM, 2MX16, 55ns, CMOS, PDSO48,
CY62177EV18LL-70BAXI	CYPRESS	获取价格	Standard SRAM, 2MX16, 70ns, CMOS, PBGA48, 8 X 9.50 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-48
CY62177EV18LL-70BAXI	INFINEON	获取价格	Asynchronous SRAM

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