Datasheet > CY62177EV18LL-70BAXI

CY62177EV18LL-70BAXI

更新时间： 2024-11-19 14:56:35

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
17页	357K
描述
Asynchronous SRAM

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CY62177EV18 MoBL^®

32-Mbit (2 M × 16 / 4 M × 8) Static RAM

32-Mbit (2

M × 16 / 4 M × 8) Static RAM

Features

Functional Description

■ Thin small outline package (TSOP) I configurable as 2 M × 16

or as 4 M × 8 static RAM (SRAM)

The CY62177EV18 is a high-performance CMOS static RAM

organized as 2 M words by 16 bits and 4 M words by 8 bits. This

device features advanced circuit design to provide ultra low

active current. It is ideal for providing More Battery Life

(MoBL^®) in portable applications, such as cellular telephones.

The device also has an automatic power-down feature that

significantly reduces power consumption by 99 percent when

addresses are not toggling. The device can also be put into

standby mode when deselected (CE₁HIGH or CE₂LOW or both

BHE and BLE are HIGH). The input and output pins (I/O₀through

I/O₁₅) are placed in a high impedance state when: deselected

(CE₁HIGH or CE₂LOW), outputs are disabled (OE HIGH), both

Byte High Enable and Byte Low Enable are disabled (BHE, BLE

HIGH), or during a write operation (CE₁LOW, CE₂HIGH and WE

LOW).

■ Very high speed

❐ 70 ns

■ Wide voltage range

❐ 1.65 V to 2.25 V

■ Ultra low standby power

❐ Typical standby current: 3 A

❐ Maximum standby current: 25 A

■ Ultra low active power

❐ Typical active current: 4.5 mA at f = 1 MHz

■ Easy memory expansion with CE₁, CE_2,and OE Features

■ Automatic power-down when deselected

To write to the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇), is

written into the location specified on the address pins (A₀through

A₂₀). If Byte High Enable (BHE) is LOW, then data from I/O pins

(I/O₈through I/O₁₅) is written to the location specified on the

address pins (A₀through A₂₀). To read from the device, take

Chip Enables (CE₁LOW and CE₂HIGH) and Output Enable

(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte

Low Enable (BLE) is LOW, then data from the memory location

specified by the address pins appear on I/O₀to I/O₇. If Byte High

Enable (BHE) is LOW, then data from memory appears on I/O₈

to I/O₁₅. See the Truth Table on page 11 for a complete

description of read and write modes.

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed and power

■ Available in Pb-free 48-ball TSOP I and 48-ball FBGA package

Pin #13 of the 48 TSOP I package is an DNU pin that must be

left floating at all times to ensure proper application.

For a complete list of related documentation, click here.

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

A ₄

A ₃

2M × 16

RAM Array

I/O₀–I/O₇

I/O₈–I/O₁₅

A ₂

A ₁

A ₀

COLUMN DECODER

BYTE

BHE

CE₂

CE₁

BLE

Power-Down

Circuit

CE₂

CE₁

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 001-76091 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 28, 2014

12 3 4 5 6 7...17

中文翻译

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与CY62177EV18LL-70BAXI相关器件

型号	品牌	获取价格	描述	数据表
CY62177EV18LL-70BAXIT	CYPRESS	获取价格	Standard SRAM, 2MX16, 70ns, CMOS, PBGA48,
CY62177EV18LL-70BAXIT	INFINEON	获取价格	Asynchronous SRAM
CY62177EV30	CYPRESS	获取价格	32-Mbit (2 M x 16 / 4 M x 8) Static RAM Automatic power down when deselected
CY62177EV30_11	CYPRESS	获取价格	32-Mbit (2 M x 16 / 4 M x 8) Static RAM Automatic power down when deselected
CY62177EV30LL	CYPRESS	获取价格	32-Mbit (2 M Ã 16 / 4 M Ã 8) Static RAM
CY62177EV30LL-55BAXI	CYPRESS	获取价格	暂无描述
CY62177EV30LL-55BAXI	INFINEON	获取价格	Asynchronous SRAM
CY62177EV30LL-55BAXIT	CYPRESS	获取价格	Standard SRAM, 2MX16, 55ns, CMOS, PBGA48,
CY62177EV30LL-55BAXIT	INFINEON	获取价格	Asynchronous SRAM
CY62177EV30LL-55ZXI	CYPRESS	获取价格	32-Mbit (2 M x 16 / 4 M x 8) Static RAM Automatic power down when deselected

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