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CY62177EV18LL-70BAXI

更新时间： 2024-11-05 19:54:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
17页 366K
描述
Standard SRAM, 2MX16, 70ns, CMOS, PBGA48, 8 X 9.50 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-48

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CY62177EV18LL-70BAXI 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TFBGA,Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：2.3
最长访问时间：70 nsJESD-30 代码：R-PBGA-B48
JESD-609代码：e1长度：9.5 mm
内存密度：33554432 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：48
字数：2097152 words字数代码：2000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：2MX16
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
座面最大高度：1.2 mm最大供电电压 (Vsup)：2.25 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN SILVER COPPER
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：40
宽度：8 mmBase Number Matches：1

CY62177EV18LL-70BAXI 数据手册

 浏览型号CY62177EV18LL-70BAXI的Datasheet PDF文件第2页浏览型号CY62177EV18LL-70BAXI的Datasheet PDF文件第3页浏览型号CY62177EV18LL-70BAXI的Datasheet PDF文件第4页浏览型号CY62177EV18LL-70BAXI的Datasheet PDF文件第5页浏览型号CY62177EV18LL-70BAXI的Datasheet PDF文件第6页浏览型号CY62177EV18LL-70BAXI的Datasheet PDF文件第7页 
CY62177EV18 MoBL®  
32-Mbit (2 M × 16 / 4 M × 8) Static RAM  
32-Mbit (2  
M × 16 / 4 M × 8) Static RAM  
Features  
Functional Description  
■ Thin small outline package (TSOP) I configurable as 2 M × 16  
or as 4 M × 8 static RAM (SRAM)  
The CY62177EV18 is a high-performance CMOS static RAM  
organized as 2 M words by 16 bits and 4 M words by 8 bits. This  
device features advanced circuit design to provide ultra low  
active current. It is ideal for providing More Battery Life  
(MoBL®) in portable applications, such as cellular telephones.  
The device also has an automatic power-down feature that  
significantly reduces power consumption by 99 percent when  
addresses are not toggling. The device can also be put into  
standby mode when deselected (CE1 HIGH or CE2 LOW or both  
BHE and BLE are HIGH). The input and output pins (I/O0 through  
I/O15) are placed in a high impedance state when: deselected  
(CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both  
Byte High Enable and Byte Low Enable are disabled (BHE, BLE  
HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE  
LOW).  
■ Very high speed  
❐ 70 ns  
■ Wide voltage range  
❐ 1.65 V to 2.25 V  
■ Ultra low standby power  
❐ Typical standby current: 3 A  
❐ Maximum standby current: 25 A  
■ Ultra low active power  
❐ Typical active current: 4.5 mA at f = 1 MHz  
■ Easy memory expansion with CE1, CE2, and OE Features  
■ Automatic power-down when deselected  
To write to the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0 through  
A20). If Byte High Enable (BHE) is LOW, then data from I/O pins  
(I/O8 through I/O15) is written to the location specified on the  
address pins (A0 through A20). To read from the device, take  
Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable  
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte  
Low Enable (BLE) is LOW, then data from the memory location  
specified by the address pins appear on I/O0 to I/O7. If Byte High  
Enable (BHE) is LOW, then data from memory appears on I/O8  
to I/O15. See the Truth Table on page 11 for a complete  
description of read and write modes.  
■ Complementary metal oxide semiconductor (CMOS) for  
optimum speed and power  
■ Available in Pb-free 48-ball TSOP I and 48-ball FBGA package  
Pin #13 of the 48 TSOP I package is an DNU pin that must be  
left floating at all times to ensure proper application.  
For a complete list of related documentation, click here.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
A 3  
2M × 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A 2  
A 1  
A 0  
COLUMN DECODER  
BYTE  
BHE  
WE  
CE2  
CE1  
OE  
BLE  
Power-Down  
Circuit  
CE2  
CE1  
BHE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 001-76091 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised November 28, 2014  
 
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CY62177EV30LL-55BAXI INFINEON

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CY62177EV30LL-55BAXIT CYPRESS

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