Datasheet > CY62187EV30LL-55BAXIT

CY62187EV30LL-55BAXIT

更新时间： 2024-11-06 14:56:15

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
20页	277K
描述
Asynchronous SRAM

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CY62187EV30 MoBL^®

64-Mbit (4M × 16) Static RAM

64-Mbit (4M

× 16) Static RAM

Features

Functional Description

■ Very high speed

❐ 55 ns

CY62187EV30 is a high-performance CMOS static RAM

organized as 4M words by 16 bits. This device features an

advanced circuit design to provide ultra-low active current. It is

ideal for providing More Battery Life™ (MoBL^®) in portable

■ Wide voltage range

❐ 2.2 V to 3.6 V

applications such as cellular phones.

■ Ultra-low standby power

❐ Typical standby current: 8 A

❐ Maximum standby current: 48 A

The device also has an Automatic Power Down feature that

significantly reduces power consumption by 99 percent when

addresses are not toggling. The device can also be put into

standby mode when deselected (CE₁HIGH or CE₂LOW or both

■ Ultra-low active power

❐ Typical active current: 15 mA at f = 1 MHz

BHE and BLE are HIGH). The input and output pins (I/O₀through

I/O₁₅) are placed in a High-Z state when: deselected (CE₁HIGH

or CE₂LOW), outputs are disabled (OE HIGH), both Byte High

■ Easy memory expansion with CE₁, CE_2,and OE features

■ Automatic Power Down when deselected

■ CMOS for optimum speed and power

Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or

during a write operation (CE₁LOW, CE₂HIGH and WE LOW).

■ Available in Pb-free 48-ball FBGA package

To write to the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇), is

written into the location specified on the address pins (A₀through

A₂₁). If Byte High Enable (BHE) is LOW, then data from I/O pins

(I/O₈through I/O₁₅) is written into the location specified on the

address pins (A₀through A₂₁).

To read from the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing Write Enable

(WE) HIGH. If BLE is LOW, then data from the memory location

specified by the address pins appear on I/O₀to I/O₇. If BHE is

LOW, then data from the memory appears on I/O₈to I/O₁₅. See

the Truth Table on page 12 for a complete description of read

and write modes.

For a complete list of related documentation, click here.

Cypress Semiconductor Corporation

Document Number: 001-48998 Rev. *N

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 24, 2019

12 3 4 5 6 7...20

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与CY62187EV30LL-55BAXIT相关器件

型号	品牌	获取价格	描述	数据表
CY62187EV30LL-70BAXI	CYPRESS	获取价格	64 Mbit (4M x 16) Static RAM
CY62187G30-55BAXI	INFINEON	获取价格	Asynchronous SRAM
CY62256	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256_06	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256-55	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256-55PC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256-55SNC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256-55ZC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256-55ZRC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256-70	CYPRESS	获取价格	256K (32K x 8) Static RAM

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