Datasheet > CY62187EV30LL-55BAXI_12

CY62187EV30LL-55BAXI_12

更新时间： 2024-10-02 12:23:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
15页	270K
描述
64-Mbit (4 M Ã 16) Static RAM

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CY62187EV30LL-55BAXI_12 数据手册

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CY62187EV30 MoBL^®

64-Mbit (4 M × 16) Static RAM

shy64-Mbit (4

M × 16) Static RAM

Features

Functional Description

■ Very high speed

❐ 55 ns

The CY62187EV30 is a high performance CMOS static RAM

organized as 4 M words by 16-bits. This device features

advanced circuit design to provide ultra low active current. It is

ideal for providing More Battery Life (MoBL^®) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption by 99 percent when addresses are not toggling.

The device can also be put into standby mode when deselected

(CE₁HIGH or CE₂LOW or both BHE and BLE are HIGH). The

input and output pins (I/O₀through I/O₁₅) are placed in a high

impedance state when: deselected (CE₁HIGH or CE₂LOW),

outputs are disabled (OE HIGH), both Byte High Enable and Byte

Low Enable are disabled (BHE, BLE HIGH), or during a write

operation (CE₁LOW, CE₂HIGH and WE LOW).

■ Wide voltage range

❐ 2.2 V to 3.7 V

■ Ultra low standby power

❐ Typical standby current: 8 A

❐ Maximum standby current: 48 A

■ Ultra low active power

❐ Typical active current: 7.5 mA at f = 1 MHz

■ Easy memory expansion with CE₁, CE_2,and OE features

■ Automatic power down when deselected

■ CMOS for optimum speed and power

To write to the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇), is

written into the location specified on the address pins (A₀through

■ Available in Pb-free 48-ball FBGA package

₂₁). If Byte High Enable (BHE) is LOW, then data from I/O pins

(I/O₈through I/O₁₅) is written into the location specified on the

address pins (A₀through A₂₁).

To read from the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins appear

on I/O₀to I/O₇. If Byte High Enable (BHE) is LOW, then data from

memory appears on I/O₈to I/O₁₅. See the Truth Table on page

9 for a complete description of read and write modes.

Cypress Semiconductor Corporation

Document Number: 001-48998 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 18, 2012

12 3 4 5 6 7...15

中文翻译

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与CY62187EV30LL-55BAXI_12相关器件

型号	品牌	获取价格	描述	数据表
CY62187EV30LL-55BAXIT	CYPRESS	获取价格	Standard SRAM, 4MX16, 55ns, CMOS, PBGA48, 8 X 9.50 MM, 1.40 MM HEIGHT, LEAD FREE, MO-205,
CY62187EV30LL-55BAXIT	INFINEON	获取价格	Asynchronous SRAM
CY62187EV30LL-70BAXI	CYPRESS	获取价格	64 Mbit (4M x 16) Static RAM
CY62187G30-55BAXI	INFINEON	获取价格	Asynchronous SRAM
CY62256	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256_06	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256-55	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256-55PC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256-55SNC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256-55ZC	CYPRESS	获取价格	256K (32K x 8) Static RAM

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