Datasheet > CY62187EV30

CY62187EV30

更新时间： 2024-11-05 06:51:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	362K
描述
64 Mbit (4M x 16) Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62187EV30 数据手册

CY62187EV30, MoBL^®

64 Mbit (4M x 16) Static RAM

ideal for providing More Battery Life™ (MoBL^®) in portable appli-

cations such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption by 99 percent when addresses are not toggling.

The device can also be put into standby mode when deselected

(CE₁HIGH or CE₂LOW or both BHE and BLE are HIGH). The

input and output pins (IO₀through IO₁₅) are placed in a high

impedance state when: deselected (CE₁HIGH or CE₂LOW),

outputs are disabled (OE HIGH), both Byte High Enable and

Byte Low Enable are disabled (BHE, BLE HIGH), or during a

write operation (CE₁LOW, CE₂HIGH and WE LOW).

Features

■

Very High Speed

55 ns

Wide Voltage Range

2.2V to 3.7V

Ultra Low Standby Power

❐

Typical Standby Current: 8 μA

❐

Maximum Standby Current: 48 μA

■

Ultra Low Active Power

Typical Active Current: 4.0 mA at f = 1 MHz

To write to the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (IO₀through IO₇), is

written into the location specified on the address pins (A₀through

❐

■

Easy Memory Expansion with CE₁, CE_2,and OE Features

Automatic Power Down when Deselected

CMOS for Optimum Speed and Power

₂₁). If Byte High Enable (BHE) is LOW, then data from I/O pins

(IO₈through IO₁₅) is written into the location specified on the

address pins (A₀through A₂₁).

Available in Pb-Free 48-Ball FBGA Package

To read from the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins appear

on IO₀to IO₇. If Byte High Enable (BHE) is LOW, then data from

memory appears on IO₈to IO₁₅. See the Truth Table on page 9

for a complete description of read and write modes.

Functional Description

The CY62187EV30 is a high performance CMOS static RAM

organized as 4M words by 16 bits^[1]. This device features

advanced circuit design to provide ultra low active current. It is

Logic Block Diagram

DATA-IN DRIVERS

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

A ₄

A ₃

4096K × 16

RAM Array

I/O₀–I/O₇

I/O₈–I/O₁₅

A ₂

A ₁

A ₀

COLUMN DECODER

BHE

CE₂

BLE

Power-down

Circuit

Note

1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 001-48998 Rev. *C

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised July 10, 2009

[+] Feedback

12 3 4 5 6 7...12

中文翻译

下载PDF

与CY62187EV30相关器件

型号	品牌	获取价格	描述	数据表
CY62187EV30_11	CYPRESS	获取价格	64-Mbit (4 M × 16) Static RAM
CY62187EV30_1106	CYPRESS	获取价格	64-Mbit (4 M x 16) Static RAM Ultra low standby power
CY62187EV30_12	CYPRESS	获取价格	64-Mbit (4 M Ã 16) Static RAM
CY62187EV30LL	CYPRESS	获取价格	64-Mbit (4 M × 16) Static RAM
CY62187EV30LL-55BAXI	CYPRESS	获取价格	64 Mbit (4M x 16) Static RAM
CY62187EV30LL-55BAXI	INFINEON	获取价格	Asynchronous SRAM
CY62187EV30LL-55BAXI_12	CYPRESS	获取价格	64-Mbit (4 M Ã 16) Static RAM
CY62187EV30LL-55BAXIT	CYPRESS	获取价格	Standard SRAM, 4MX16, 55ns, CMOS, PBGA48, 8 X 9.50 MM, 1.40 MM HEIGHT, LEAD FREE, MO-205,
CY62187EV30LL-55BAXIT	INFINEON	获取价格	Asynchronous SRAM
CY62187EV30LL-70BAXI	CYPRESS	获取价格	64 Mbit (4M x 16) Static RAM

与CY62187EV30相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

13
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

9
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

35
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

31

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62187EV30

CY62187EV30 数据手册

与CY62187EV30相关器件

与CY62187EV30相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62187EV30

CY62187EV30 数据手册

与CY62187EV30相关器件

与CY62187EV30相关文章

您还可以找

您在本页遇到什么问题？