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CY62187EV30LL-55BAXI PDF预览

CY62187EV30LL-55BAXI

更新时间： 2024-11-16 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
12页 362K
描述
64 Mbit (4M x 16) Static RAM

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中文翻译

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CY62187EV30LL-55BAXI 技术参数

是否Rohs认证：符合生命周期：Active
零件包装代码：BGA包装说明：LFBGA, BGA48,6X8,30
针数：48Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：1.38Is Samacsys：N
最长访问时间：55 nsI/O 类型：COMMON
JESD-30 代码：R-PBGA-B48JESD-609代码：e1
长度：9.5 mm内存密度：67108864 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：48字数：4194304 words
字数代码：4000000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：4MX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装等效代码：BGA48,6X8,30封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5/3.3 V
认证状态：Not Qualified座面最大高度：1.5 mm
最大待机电流：0.000048 A最小待机电流：1.5 V
子类别：SRAMs最大压摆率：0.055 mA
最大供电电压 (Vsup)：3.7 V最小供电电压 (Vsup)：2.2 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：40宽度：8 mm
Base Number Matches：1

CY62187EV30LL-55BAXI 数据手册

 浏览型号CY62187EV30LL-55BAXI的Datasheet PDF文件第2页浏览型号CY62187EV30LL-55BAXI的Datasheet PDF文件第3页浏览型号CY62187EV30LL-55BAXI的Datasheet PDF文件第4页浏览型号CY62187EV30LL-55BAXI的Datasheet PDF文件第5页浏览型号CY62187EV30LL-55BAXI的Datasheet PDF文件第6页浏览型号CY62187EV30LL-55BAXI的Datasheet PDF文件第7页 
CY62187EV30, MoBL®  
64 Mbit (4M x 16) Static RAM  
ideal for providing More Battery Life™ (MoBL®) in portable appli-  
cations such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption by 99 percent when addresses are not toggling.  
The device can also be put into standby mode when deselected  
(CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The  
input and output pins (IO0 through IO15) are placed in a high  
impedance state when: deselected (CE1HIGH or CE2 LOW),  
outputs are disabled (OE HIGH), both Byte High Enable and  
Byte Low Enable are disabled (BHE, BLE HIGH), or during a  
write operation (CE1 LOW, CE2 HIGH and WE LOW).  
Features  
■
■
■
Very High Speed  
55 ns  
Wide Voltage Range  
2.2V to 3.7V  
Ultra Low Standby Power  
❐
❐
❐
Typical Standby Current: 8 μA  
❐
Maximum Standby Current: 48 μA  
■
Ultra Low Active Power  
Typical Active Current: 4.0 mA at f = 1 MHz  
To write to the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (IO0 through IO7), is  
written into the location specified on the address pins (A0 through  
❐
■
■
■
■
Easy Memory Expansion with CE1, CE2, and OE Features  
Automatic Power Down when Deselected  
CMOS for Optimum Speed and Power  
A
21). If Byte High Enable (BHE) is LOW, then data from I/O pins  
(IO8 through IO15) is written into the location specified on the  
address pins (A0 through A21).  
Available in Pb-Free 48-Ball FBGA Package  
To read from the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins appear  
on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from  
memory appears on IO8 to IO15. See the Truth Table on page 9  
for a complete description of read and write modes.  
Functional Description  
The CY62187EV30 is a high performance CMOS static RAM  
organized as 4M words by 16 bits[1]. This device features  
advanced circuit design to provide ultra low active current. It is  
Logic Block Diagram  
DATA-IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
A 3  
4096K × 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A 2  
A 1  
A 0  
COLUMN DECODER  
BHE  
WE  
CE2  
CE  
1
OE  
BLE  
Power-down  
Circuit  
Note  
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-48998 Rev. *C  
•
198 Champion Court  
•
San Jose  
,
CA 95134-1709  
•
408-943-2600  
Revised July 10, 2009  
[+] Feedback  
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中文翻译

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CY62187EV30LL-55BAXI 替代型号

型号 品牌 替代类型 描述 数据表
CY62187EV30LL-55BAXIT CYPRESS

完全替代

 Standard SRAM, 4MX16, 55ns, CMOS, PBGA48, 8 X 9.50 MM, 1.40 MM HEIGHT, LEAD FREE, MO-205,
CY62177EV30LL-55BAXI CYPRESS

类似代替

 暂无描述
CY7C1071DV33-12BAXI CYPRESS

类似代替

 32-Mbit (2 M x 16) Static RAM TTL compatible inputs and outputs

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CY62187EV30LL-55BAXIT CYPRESS

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