5秒后页面跳转
捷配首页

Datasheet > CY62177ESL-55ZXI
CY62177ESL-55ZXI PDF预览

CY62177ESL-55ZXI

更新时间： 2024-11-21 18:11:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
16页 382K
描述
Standard SRAM, 2MX16, 55ns, CMOS, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, LEAD FREE, MO-142, TSOP1-48

阅读下载

中文翻译

获取价格

CY62177ESL-55ZXI 技术参数

是否Rohs认证： 符合生命周期：End Of Life
零件包装代码：TSOP1包装说明：TSOP1, TSSOP48,.8,20
针数：48Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.73
最长访问时间：55 ns其他特性：ALSO OPERATES AT 5V SUPPLY
备用内存宽度：8I/O 类型：COMMON
JESD-30 代码：R-PDSO-G48JESD-609代码：e3
长度：18.4 mm内存密度：33554432 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：48字数：2097152 words
字数代码：2000000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：2MX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP1
封装等效代码：TSSOP48,.8,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5/3.3,5 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.000017 A最小待机电流：1.5 V
子类别：SRAMs最大压摆率：0.045 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.2 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：12 mm
Base Number Matches：1

CY62177ESL-55ZXI 数据手册

 浏览型号CY62177ESL-55ZXI的Datasheet PDF文件第2页浏览型号CY62177ESL-55ZXI的Datasheet PDF文件第3页浏览型号CY62177ESL-55ZXI的Datasheet PDF文件第4页浏览型号CY62177ESL-55ZXI的Datasheet PDF文件第5页浏览型号CY62177ESL-55ZXI的Datasheet PDF文件第6页浏览型号CY62177ESL-55ZXI的Datasheet PDF文件第7页 
CY62177ESL MoBL®  
32-Mbit (2 M × 16/4 M × 8) Static RAM  
32-Mbit (2  
M × 16/4 M × 8) Static RAM  
Features  
Functional Description  
■ Thin small outline package-I (TSOP-I) configurable as  
2 M × 16 or as 4 M × 8 static RAM (SRAM)  
The CY62177ESL is a high performance CMOS static RAM  
organized as 2 M words by 16 bits and 4 M words by 8 bits. This  
device features advanced circuit design to provide ultra low  
active current. It is ideal for providing More Battery Life  
(MoBL®) in portable applications such as cellular telephones.  
The device also has an automatic power-down feature that  
significantly reduces power consumption by 99 percent when  
addresses are not toggling. The device can also be put into  
standby mode when deselected (CE1 HIGH or CE2 LOW or both  
BHE and BLE are HIGH). The input and output pins (I/O0 through  
I/O15) are placed in a high impedance state when: deselected  
(CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both  
Byte High Enable and Byte Low Enable are disabled (BHE, BLE  
HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE  
LOW).  
■ High-speed up to 55 ns  
■ Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V  
■ Ultra low standby power  
❐ Typical standby current: 3 µA  
❐ Maximum standby current: 25 µA  
■ Ultra low active power  
❐ Typical active current: 4.5 mA at f = 1 MHz  
■ Easy memory expansion with CE1, CE2, and OE Features  
■ Automatic power-down when deselected  
To write to the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0 through  
■ Complementary metal oxide semiconductor (CMOS) for  
optimum speed and power  
■ Available in Pb-free 48-ball TSOP-I package  
A20). If Byte High Enable (BHE) is LOW, then data from I/O pins  
(I/O8 through I/O15) is written to the location specified on the  
address pins (A0 through A20). To read from the device, take  
Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable  
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte  
Low Enable (BLE) is LOW, then data from the memory location  
specified by the address pins appear on I/O0 to I/O7. If Byte High  
Enable (BHE) is LOW, then data from memory appears on I/O8  
to I/O15. See the Truth Table on page 11 for a complete  
description of read and write modes.  
For a complete list of related documentation, click here.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
A 3  
2 M × 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A 2  
A 1  
A 0  
COLUMN DECODER  
BYTE  
BHE  
WE  
CE2  
CE1  
OE  
BLE  
Power-down  
Circuit  
CE2  
CE1  
BHE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 001-64709 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
• 408-943-2600  
Revised November 17, 2015  
 
1234567...16

中文翻译

下载PDF

CY62177ESL-55ZXI 替代型号

型号 品牌 替代类型 描述 数据表
CY62177EV30LL-55ZXIT CYPRESS

类似代替

 Standard SRAM, 2MX16, 55ns, CMOS, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, LEAD FREE, MO-142, T
CY62177EV30LL-55ZXI CYPRESS

类似代替

 32-Mbit (2 M x 16 / 4 M x 8) Static RAM Automatic power down when deselected

与CY62177ESL-55ZXI相关器件

型号 品牌 获取价格 描述 数据表
CY62177ESL-55ZXIT CYPRESS

获取价格

 		Standard SRAM, 2MX16, 55ns, CMOS, PDSO48,
CY62177EV18LL-70BAXI CYPRESS

获取价格

 		Standard SRAM, 2MX16, 70ns, CMOS, PBGA48, 8 X 9.50 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-48
CY62177EV18LL-70BAXI INFINEON

获取价格

 		Asynchronous SRAM
CY62177EV18LL-70BAXIT CYPRESS

获取价格

 		Standard SRAM, 2MX16, 70ns, CMOS, PBGA48,
CY62177EV18LL-70BAXIT INFINEON

获取价格

 		Asynchronous SRAM
CY62177EV30 CYPRESS

获取价格

 		32-Mbit (2 M x 16 / 4 M x 8) Static RAM Automatic power down when deselected
CY62177EV30_11 CYPRESS

获取价格

 		32-Mbit (2 M x 16 / 4 M x 8) Static RAM Automatic power down when deselected
CY62177EV30LL CYPRESS

获取价格

 		32-Mbit (2 M × 16 / 4 M × 8) Static RAM
CY62177EV30LL-55BAXI CYPRESS

获取价格

 		暂无描述
CY62177EV30LL-55BAXI INFINEON

获取价格

 		Asynchronous SRAM

与CY62177ESL-55ZXI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证