5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> CY62177DV30LL-55BAI
CY62177DV30LL-55BAI PDF预览

CY62177DV30LL-55BAI

更新时间： 2024-11-05 04:53:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 930K
描述
16-Mbit (2M x 8) Static RAM

阅读下载

中文翻译

获取价格

CY62177DV30LL-55BAI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：TFBGA, BGA48,6X8,30针数：48
Reach Compliance Code：not_compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.76
Base Number Matches：1

CY62177DV30LL-55BAI 数据手册

 浏览型号CY62177DV30LL-55BAI的Datasheet PDF文件第2页浏览型号CY62177DV30LL-55BAI的Datasheet PDF文件第3页浏览型号CY62177DV30LL-55BAI的Datasheet PDF文件第4页浏览型号CY62177DV30LL-55BAI的Datasheet PDF文件第5页浏览型号CY62177DV30LL-55BAI的Datasheet PDF文件第6页浏览型号CY62177DV30LL-55BAI的Datasheet PDF文件第7页 
CY62168EV30 MoBL®  
16-Mbit (2M x 8) Static RAM  
toggling. Placing the device into standby mode reduces power  
consumption by more than 99% when deselected (Chip  
Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW). The input  
and output pins (IO0 through IO7) are placed in a high  
impedance state when: the device is deselected (Chip Enable  
1 (CE1) HIGH or Chip Enable 2 (CE2) LOW), outputs are  
disabled (OE HIGH), or a write operation is in progress (Chip  
Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE  
LOW).  
Features  
• Very high speed: 45 ns  
• Wide voltage range: 2.20V – 3.60V  
• Ultra low standby power  
— Typical standby current: 1.5 µA  
— Maximum standby current: 12 µA  
• Ultra low active power  
Write to the device by taking Chip Enable 1 (CE1) LOW and  
Chip Enable 2 (CE2) HIGH and the Write Enable (WE) input  
LOW. Data on the eight IO pins (IO0 through IO7) is then  
written into the location specified on the address pins (A0  
through A20).  
— Typical active current: 2.2 mA @ f = 1 MHz  
• Easy memory expansion with CE1, CE2 and OE features  
• Automatic power down when deselected  
• CMOS for optimum speed/power  
Read from the device by taking Chip Enable 1 (CE1) and  
Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH  
while forcing Write Enable (WE) HIGH. Under these condi-  
tions, the contents of the memory location specified by the  
address pins will appear on the IO pins.  
• Offered in Pb-free 48-ball FBGA package. For Pb-free  
48-pin TSOP I package, refer to CY62167EV30 data sheet.  
Functional Description[1]  
The CY62168EV30 is a high performance CMOS static RAM  
organized as 2M words by 8 bits. This device features  
advanced circuit design to provide an ultra low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
also has an automatic power down feature that significantly  
reduces power consumption by 90% when addresses are not  
The eight input and output pins (IO0 through IO7) are placed  
in a high impedance state when the device is deselected (CE1  
LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or  
a write operation is in progress (CE1 LOW and CE2 HIGH and  
WE LOW). See the “Truth Table” on page 8 for a complete  
description of read and write modes.  
Logic Block Diagram  
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO  
0
DATA IN DRIVERS  
IO  
1
IO  
2
2M x 8  
IO  
3
IO  
IO  
IO  
IO  
ARRAY  
4
5
6
7
A
A
A
A
9
10  
11  
12  
CE  
CE  
1
2
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Note  
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.  
Cypress Semiconductor Corporation  
Document #: 001-07721 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 07, 2007  
[+] Feedback  
1234567...10

中文翻译

下载PDF

与CY62177DV30LL-55BAI相关器件

型号 品牌 获取价格 描述 数据表
CY62177DV30LL-55BAXI CYPRESS

获取价格

 		16-Mbit (2M x 8) Static RAM
CY62177ESL-55ZXI CYPRESS

获取价格

 		Standard SRAM, 2MX16, 55ns, CMOS, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, LEAD FREE, MO-142, T
CY62177ESL-55ZXIT CYPRESS

获取价格

 		Standard SRAM, 2MX16, 55ns, CMOS, PDSO48,
CY62177EV18LL-70BAXI CYPRESS

获取价格

 		Standard SRAM, 2MX16, 70ns, CMOS, PBGA48, 8 X 9.50 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-48
CY62177EV18LL-70BAXI INFINEON

获取价格

 		Asynchronous SRAM
CY62177EV18LL-70BAXIT CYPRESS

获取价格

 		Standard SRAM, 2MX16, 70ns, CMOS, PBGA48,
CY62177EV18LL-70BAXIT INFINEON

获取价格

 		Asynchronous SRAM
CY62177EV30 CYPRESS

获取价格

 		32-Mbit (2 M x 16 / 4 M x 8) Static RAM Automatic power down when deselected
CY62177EV30_11 CYPRESS

获取价格

 		32-Mbit (2 M x 16 / 4 M x 8) Static RAM Automatic power down when deselected
CY62177EV30LL CYPRESS

获取价格

 		32-Mbit (2 M × 16 / 4 M × 8) Static RAM

与CY62177DV30LL-55BAI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证