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CY62177DV30LL-55BAI PDF预览

CY62177DV30LL-55BAI

更新时间： 2024-11-18 04:53:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 930K
描述
16-Mbit (2M x 8) Static RAM

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中文翻译

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CY62177DV30LL-55BAI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：TFBGA, BGA48,6X8,30针数：48
Reach Compliance Code：not_compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.76
Base Number Matches：1

CY62177DV30LL-55BAI 数据手册

 浏览型号CY62177DV30LL-55BAI的Datasheet PDF文件第2页浏览型号CY62177DV30LL-55BAI的Datasheet PDF文件第3页浏览型号CY62177DV30LL-55BAI的Datasheet PDF文件第4页浏览型号CY62177DV30LL-55BAI的Datasheet PDF文件第5页浏览型号CY62177DV30LL-55BAI的Datasheet PDF文件第6页浏览型号CY62177DV30LL-55BAI的Datasheet PDF文件第7页 
CY62168EV30 MoBL®  
16-Mbit (2M x 8) Static RAM  
toggling. Placing the device into standby mode reduces power  
consumption by more than 99% when deselected (Chip  
Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW). The input  
and output pins (IO0 through IO7) are placed in a high  
impedance state when: the device is deselected (Chip Enable  
1 (CE1) HIGH or Chip Enable 2 (CE2) LOW), outputs are  
disabled (OE HIGH), or a write operation is in progress (Chip  
Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE  
LOW).  
Features  
• Very high speed: 45 ns  
• Wide voltage range: 2.20V – 3.60V  
• Ultra low standby power  
— Typical standby current: 1.5 µA  
— Maximum standby current: 12 µA  
• Ultra low active power  
Write to the device by taking Chip Enable 1 (CE1) LOW and  
Chip Enable 2 (CE2) HIGH and the Write Enable (WE) input  
LOW. Data on the eight IO pins (IO0 through IO7) is then  
written into the location specified on the address pins (A0  
through A20).  
— Typical active current: 2.2 mA @ f = 1 MHz  
• Easy memory expansion with CE1, CE2 and OE features  
• Automatic power down when deselected  
• CMOS for optimum speed/power  
Read from the device by taking Chip Enable 1 (CE1) and  
Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH  
while forcing Write Enable (WE) HIGH. Under these condi-  
tions, the contents of the memory location specified by the  
address pins will appear on the IO pins.  
• Offered in Pb-free 48-ball FBGA package. For Pb-free  
48-pin TSOP I package, refer to CY62167EV30 data sheet.  
Functional Description[1]  
The CY62168EV30 is a high performance CMOS static RAM  
organized as 2M words by 8 bits. This device features  
advanced circuit design to provide an ultra low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
also has an automatic power down feature that significantly  
reduces power consumption by 90% when addresses are not  
The eight input and output pins (IO0 through IO7) are placed  
in a high impedance state when the device is deselected (CE1  
LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or  
a write operation is in progress (CE1 LOW and CE2 HIGH and  
WE LOW). See the “Truth Table” on page 8 for a complete  
description of read and write modes.  
Logic Block Diagram  
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO  
0
DATA IN DRIVERS  
IO  
1
IO  
2
2M x 8  
IO  
3
IO  
IO  
IO  
IO  
ARRAY  
4
5
6
7
A
A
A
A
9
10  
11  
12  
CE  
CE  
1
2
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Note  
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.  
Cypress Semiconductor Corporation  
Document #: 001-07721 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised June 07, 2007  
[+] Feedback  
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