Datasheet > CY62177DV30_09

CY62177DV30_09

更新时间： 2024-11-05 06:51:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	499K
描述
32-Mbit (2M x 16) Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62177DV30_09 数据手册

CY62177DV30

MoBL^®

32-Mbit (2M x 16) Static RAM

reduces power consumption. The device can also be put into

standby mode when deselected (CE₁HIGH or CE₂LOW or

both BHE and BLE are HIGH). The input/output pins (I/O₀

through I/O₁₅) are placed in a high-impedance state when:

deselected (CE₁HIGH or CE₂LOW), outputs are disabled (OE

HIGH), both Byte High Enable and Byte Low Enable are

disabled (BHE, BLE HIGH), or during a write operation (CE₁

LOW, CE₂HIGH and WE LOW).

Features

• Very high speed: 55 ns and 70 ns

• Wide voltage range: 2.20V–3.60V

• Ultra-low active power

— Typical active current: 2 mA @ f = 1 MHz

— Typical active current: 15 mA @ f = f_max

• Ultra low standby power

Writing to the device is accomplished by taking Chip Enables

(CE₁LOW and CE₂HIGH) and Write Enable (WE) input LOW.

If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O₀

through I/O₇), is written into the location specified on the

address pins (A₀through A₂₀). If Byte High Enable (BHE) is

LOW, then data from I/O pins (I/O₈through I/O₁₅) is written into

the location specified on the address pins (A₀through A₂₀).

• Easy memory expansion with CE₁, CE₂and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Packages offered in a 48-ball FBGA

Reading from the device is accomplished by taking Chip

Enables (CE₁LOW and CE₂HIGH) and Output Enable (OE)

LOW while forcing the Write Enable (WE) HIGH. If Byte Low

Enable (BLE) is LOW, then data from the memory location

specified by the address pins will appear on I/O₀to I/O₇. If Byte

High Enable (BHE) is LOW, then data from memory will appear

on I/O₈to I/O₁₅. See the truth table for a complete description

of read and write modes.

Functional Description^[1]

The CY62177DV30 is a high-performance CMOS static RAM

organized as 2M words by 16 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL^®) in

portable applications such as cellular telephones.The device

also has an automatic power-down feature that significantly

Logic Block Diagram

DATA-IN DRIVERS

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

A ₄

A ₃

2048K × 16

RAM Array

I/O₀–I/O₇

I/O₈–I/O₁₅

A ₂

A ₁

A ₀

COLUMN DECODER

BHE

CE₂

BLE

Power-down

Circuit

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05633 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 14, 2006

[+] Feedback

12 3 4 5 6 7...11

中文翻译

下载PDF

与CY62177DV30_09相关器件

型号	品牌	获取价格	描述	数据表
CY62177DV30_11	CYPRESS	获取价格	32-Mbit (2M x 16) Static RAM
CY62177DV30_12	CYPRESS	获取价格	32-Mbit (2 M Ã 16) Static RAM
CY62177DV30L-55BAI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177DV30L-70BAI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177DV30LL	CYPRESS	获取价格	32-Mbit (2M x 16) Static RAM
CY62177DV30LL-55BAI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177DV30LL-55BAXI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177ESL-55ZXI	CYPRESS	获取价格	Standard SRAM, 2MX16, 55ns, CMOS, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, LEAD FREE, MO-142, T
CY62177ESL-55ZXIT	CYPRESS	获取价格	Standard SRAM, 2MX16, 55ns, CMOS, PDSO48,
CY62177EV18LL-70BAXI	CYPRESS	获取价格	Standard SRAM, 2MX16, 70ns, CMOS, PBGA48, 8 X 9.50 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-48

与CY62177DV30_09相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

13
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

9
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

35
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

31

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62177DV30_09

CY62177DV30_09 数据手册

与CY62177DV30_09相关器件

与CY62177DV30_09相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62177DV30_09

CY62177DV30_09 数据手册

与CY62177DV30_09相关器件

与CY62177DV30_09相关文章

您还可以找

您在本页遇到什么问题？