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CY62177DV30_09 PDF预览

CY62177DV30_09

更新时间: 2024-11-18 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 499K
描述
32-Mbit (2M x 16) Static RAM

CY62177DV30_09 数据手册

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CY62177DV30  
MoBL®  
32-Mbit (2M x 16) Static RAM  
reduces power consumption. The device can also be put into  
standby mode when deselected (CE1 HIGH or CE2 LOW or  
both BHE and BLE are HIGH). The input/output pins (I/O0  
through I/O15) are placed in a high-impedance state when:  
deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE  
HIGH), both Byte High Enable and Byte Low Enable are  
disabled (BHE, BLE HIGH), or during a write operation (CE1  
LOW, CE2 HIGH and WE LOW).  
Features  
• Very high speed: 55 ns and 70 ns  
• Wide voltage range: 2.20V–3.60V  
• Ultra-low active power  
— Typical active current: 2 mA @ f = 1 MHz  
— Typical active current: 15 mA @ f = fmax  
• Ultra low standby power  
Writing to the device is accomplished by taking Chip Enables  
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.  
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0  
through I/O7), is written into the location specified on the  
address pins (A0 through A20). If Byte High Enable (BHE) is  
LOW, then data from I/O pins (I/O8 through I/O15) is written into  
the location specified on the address pins (A0 through A20).  
• Easy memory expansion with CE1, CE2 and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Packages offered in a 48-ball FBGA  
Reading from the device is accomplished by taking Chip  
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)  
LOW while forcing the Write Enable (WE) HIGH. If Byte Low  
Enable (BLE) is LOW, then data from the memory location  
specified by the address pins will appear on I/O0 to I/O7. If Byte  
High Enable (BHE) is LOW, then data from memory will appear  
on I/O8 to I/O15. See the truth table for a complete description  
of read and write modes.  
Functional Description[1]  
The CY62177DV30 is a high-performance CMOS static RAM  
organized as 2M words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life(MoBL®) in  
portable applications such as cellular telephones.The device  
also has an automatic power-down feature that significantly  
Logic Block Diagram  
DATA-IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
A 3  
2048K × 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A 2  
A 1  
A 0  
COLUMN DECODER  
BHE  
WE  
CE2  
CE  
1
OE  
BLE  
Power-down  
Circuit  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05633 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 14, 2006  
[+] Feedback  

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