CY62168G/CY62168GE MoBL®
16-Mbit (2M words × 8 bits) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (2M words
× 8 bits) Static RAM with Error-Correcting Code (ECC)
Devices with a single chip enable input are accessed by
asserting the chip enable input (CE) LOW. Dual chip enable
devices are accessed by asserting both chip enable inputs – CE1
as LOW and CE2 as HIGH.
Features
■ Ultra-low standby power
❐ Typical standby current: 5.5 A
❐ Maximum standby current: 16 A
Write to the device by taking Chip Enable 1 (CE1) LOW and
Chip Enable 2 (CE2) HIGH and the Write Enable (WE) input
LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written
■ High speed: 45 ns/55 ns
into the location specified on the address pins (A0 through A20).
■ Embedded error-correcting code (ECC) for single-bit error
correction
Read from the device by taking Chip Enable 1 (CE1) and
Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while
forcing Write Enable (WE) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
will appear on the I/O pins.
■ Widevoltage range: 1.65 V to2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V
■ 1.0 V data retention
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ ERR pin to indicate 1-bit error detection and correction
■ Available in Pb-free 48-ball VFBGA package
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a
write operation is in progress (CE1 LOW and CE2 HIGH and WE
LOW). See the Truth Table – CY62168G/CY62168GE on page
14 for a complete description of read and write modes.
Functional Description
CY62168G and CY62168GE are high-performance CMOS
low-power (MoBL) SRAM devices with embedded ECC. Both
devices are offered in single and dual chip enable options and in
multiple pin configurations. The CY62168GE device includes an
error indication pin that signals a single-bit error-detection and
correction event during a read cycle.
On CY62168GE devices, the detection and correction of a single
bit error in the accessed location is indicated by the assertion of
the ERR output (ERR = HIGH) [1]
.
The CY62168G and CY62168GE devices are available in a
Pb-free 48-pin VFBGA package. The logic block diagrams are
on page 2.
For a complete list of related resources, click here.
Product Portfolio
Power Dissipation
Features and Options
(see Pin
Operating ICC, (mA)
Speed
Product
Range
VCC Range (V)
Standby, ISB2 (µA)
(ns)
Configurations
section)
f = fmax
Typ[2]
Max
32
Typ[2]
7
Max
26
CY62168G(E)18 Single or dual Chip
Industrial
1.65 V–2.2 V
2.2 V–3.6 V
4.5 V–5.5 V
55
45
29
29
Enables
CY62168G(E)30
36
5.5
16
Optional ERR pin
CY62168G(E)
Notes
1. This device does not support automatic write-back on error detection.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for V range of 1.65 V–2.2 V), V = 3 V
CC
CC
CC
(for V range of 2.2 V–3.6 V), and V = 5 V (for V range of 4.5 V–5.5 V), T = 25 °C.
CC
CC
CC
A
Cypress Semiconductor Corporation
Document Number: 001-84771 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 22, 2017