Datasheet > CY62168GN30-45BVXI

CY62168GN30-45BVXI

更新时间： 2024-11-19 11:12:59

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器内存集成电路
页数	文件大小	规格书
17页	900K
描述
Asynchronous SRAM

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CY62168GN30 MoBL

16-Mbit (2M words × 8 bits) Static RAM

16-Mbit (2M words

× 8 bits) Static RAM

devices are accessed by asserting both chip enable inputs – CE₁

as LOW and CE₂as HIGH.

Features

■ Ultra-low standby power

❐ Typical standby current: 1.5 A

❐ Maximum standby current: 8 A

Write to the device by taking Chip Enable 1 (CE₁) LOW and

Chip Enable 2 (CE₂) HIGH and the Write Enable (WE) input

LOW. Data on the eight I/O pins (I/O₀through I/O₇) is then written

into the location specified on the address pins (A₀through A₂₀).

■ High speed: 45 ns

Read from the device by taking Chip Enable 1 (CE₁) and

Output Enable (OE) LOW and Chip Enable 2 (CE₂) HIGH while

forcing Write Enable (WE) HIGH. Under these conditions, the

contents of the memory location specified by the address pins

■ Wide voltage range: 2.2 V to 3.6 V

■ 1.0 V data retention

■ Transistor-transistor logic (TTL) compatible inputs and outputs

■ Available in Pb-free 48-ball VFBGA package

will appear on the I/O pins.

The eight input and output pins (I/O₀through I/O₇) are placed in

a high impedance state when the device is deselected (CE₁

HIGH or CE₂LOW), the outputs are disabled (OE HIGH), or a

write operation is in progress (CE₁LOW and CE₂HIGH and WE

LOW). See the Truth Table – CY62168GN30 on page 12 for a

complete description of read and write modes.

Functional Description

CY62168GN30 is high-performance CMOS low-power (MoBL)

SRAM devices. Both devices are offered in single and dual chip

enable options and in multiple pin configurations.

The CY62168GN30 device is available in a Pb-free 48-pin

VFBGA package. The logic block diagrams are on page 2.

Devices with a single chip enable input are accessed by

asserting the chip enable input (CE) LOW. Dual chip enable

Product Portfolio

Power Dissipation

Features and

Options

(see Pin

Configurations

section)

Operating I_CC, (mA)

Speed

Product

Range

V_CCRange (V)

Standby, I_SB2(µA)

(ns)

f = f_max

Typ^[2]

Max

Typ^[2]

Max

CY62168GN30^{[3, 4]}Single or dual Chip

Enables

Industrial

2.2 V–3.6 V

1.5

Notes

1. This device does not support automatic write-back on error detection.

2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 3 V (for V range of 2.2 V–3.6 V), T = 25 °C.

3. This device offers improved I , I

and I

specifications compared to the previous revision with same marketing part number.

CC SB1

SB2

4. For previous version of this device, kindly referhere. Further details about improvement and comparison between old and new versions can be found in the PCN193805.

Cypress Semiconductor Corporation

Document Number: 002-28483 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 20, 2020

12 3 4 5 6 7...17

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与CY62168GN30-45BVXI相关器件

型号	品牌	获取价格	描述	数据表
CY62168GN30-45BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62177DV20	CYPRESS	获取价格	32-Mbit (2M x 16) Static RAM
CY62177DV20_08	CYPRESS	获取价格	32-Mbit (2M x 16) Static RAM
CY62177DV20LL-70BAI	CYPRESS	获取价格	32-Mbit (2M x 16) Static RAM
CY62177DV30	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177DV30_09	CYPRESS	获取价格	32-Mbit (2M x 16) Static RAM
CY62177DV30_11	CYPRESS	获取价格	32-Mbit (2M x 16) Static RAM
CY62177DV30_12	CYPRESS	获取价格	32-Mbit (2 M Ã 16) Static RAM
CY62177DV30L-55BAI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177DV30L-70BAI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM

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