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CY62177DV20LL-70BAI PDF预览

CY62177DV20LL-70BAI

更新时间： 2024-11-18 04:53:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储静态存储器
页数 文件大小 规格书
11页 308K
描述
32-Mbit (2M x 16) Static RAM

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中文翻译

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CY62177DV20LL-70BAI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：TFBGA,
针数：48Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.92Is Samacsys：N
Base Number Matches：1

CY62177DV20LL-70BAI 数据手册

 浏览型号CY62177DV20LL-70BAI的Datasheet PDF文件第2页浏览型号CY62177DV20LL-70BAI的Datasheet PDF文件第3页浏览型号CY62177DV20LL-70BAI的Datasheet PDF文件第4页浏览型号CY62177DV20LL-70BAI的Datasheet PDF文件第5页浏览型号CY62177DV20LL-70BAI的Datasheet PDF文件第6页浏览型号CY62177DV20LL-70BAI的Datasheet PDF文件第7页 
CY62177DV20 MoBL2™  
32-Mbit (2M x 16) Static RAM  
by 99% when addresses are not toggling. The device can also  
be put into standby mode when deselected (CE1 HIGH or CE2  
LOW or both BHE and BLE are HIGH). The input and output pins  
(IO0 through IO15) are placed in a high impedance state when:  
the device is deselected (CE1HIGH or CE2 LOW); outputs are  
disabled (OE HIGH); both Byte High Enable and Byte Low  
Enable are disabled (BHE, BLE HIGH); when a write operation  
is in progress (CE1 LOW, CE2 HIGH and WE LOW).  
Features  
■ Very high speed: 70 ns  
■ Wide voltage range: 1.7V – 2.2V  
■ Ultra low active power  
❐ Typical active current: 2 mA at f = 1 MHz  
❐ Typical active current: 12 mA at f = fMAX  
To write to the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable  
(BLE) is LOW, then data from IO pins (IO0 through IO7) is written  
into the location specified on the address pins (A0 through A20).  
If Byte High Enable (BHE) is LOW, then data from IO pins (IO8  
through IO15) is written into the location specified on the address  
pins (A0 through A20).  
■ Ultra low standby power  
■ Easy memory expansion with CE1, CE2, and OE features  
■ Automatic power down when deselected  
■ CMOS for optimum speed and power  
■ Offered in 48-ball VFBGA package  
To read from the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins appears  
on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from  
memory appears on IO8 to IO15. See the Truth Table on page 9  
for a complete description of read and write modes.  
Functional Description  
The CY62177DV20 is a high performance CMOS static RAM  
organized as 2M words by 16 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL®) in portable  
applications such as cellular telephones. The device also has an  
automatic power down feature that reduces power consumption  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
2M × 16  
RAM ARRAY  
IO0–IO7  
IO8–IO15  
A 3  
A 2  
A 1  
A 0  
COLUMN DECODER  
BHE  
WE  
CE2  
CE2  
CE  
1
PowerDown  
Circuit  
CE  
1
OE  
BHE  
BLE  
BLE  
Cypress Semiconductor Corporation  
Document #: 001-44018 Rev. **  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised January 08, 2008  
[+] Feedback  
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