Datasheet > CY62177DV30

CY62177DV30

更新时间： 2024-11-05 04:53:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
10页	930K
描述
16-Mbit (2M x 8) Static RAM

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CY62177DV30 数据手册

CY62168EV30 MoBL^®

16-Mbit (2M x 8) Static RAM

toggling. Placing the device into standby mode reduces power

consumption by more than 99% when deselected (Chip

Enable 1 (CE₁) HIGH or Chip Enable 2 (CE₂) LOW). The input

and output pins (IO₀through IO₇) are placed in a high

impedance state when: the device is deselected (Chip Enable

1 (CE₁) HIGH or Chip Enable 2 (CE₂) LOW), outputs are

disabled (OE HIGH), or a write operation is in progress (Chip

Enable 1 (CE₁) LOW and Chip Enable 2 (CE₂) HIGH and WE

LOW).

Features

• Very high speed: 45 ns

• Wide voltage range: 2.20V – 3.60V

• Ultra low standby power

— Typical standby current: 1.5 µA

— Maximum standby current: 12 µA

• Ultra low active power

Write to the device by taking Chip Enable 1 (CE₁) LOW and

Chip Enable 2 (CE₂) HIGH and the Write Enable (WE) input

LOW. Data on the eight IO pins (IO₀through IO₇) is then

written into the location specified on the address pins (A₀

through A₂₀).

— Typical active current: 2.2 mA @ f = 1 MHz

• Easy memory expansion with CE₁, CE₂and OE features

• Automatic power down when deselected

• CMOS for optimum speed/power

Read from the device by taking Chip Enable 1 (CE₁) and

Output Enable (OE) LOW and Chip Enable 2 (CE₂) HIGH

while forcing Write Enable (WE) HIGH. Under these condi-

tions, the contents of the memory location specified by the

address pins will appear on the IO pins.

• Offered in Pb-free 48-ball FBGA package. For Pb-free

48-pin TSOP I package, refer to CY62167EV30 data sheet.

Functional Description^[1]

The CY62168EV30 is a high performance CMOS static RAM

organized as 2M words by 8 bits. This device features

advanced circuit design to provide an ultra low active current.

This is ideal for providing More Battery Life™ (MoBL^®) in

portable applications such as cellular telephones. The device

also has an automatic power down feature that significantly

reduces power consumption by 90% when addresses are not

The eight input and output pins (IO₀through IO₇) are placed

in a high impedance state when the device is deselected (CE₁

LOW and CE₂HIGH), the outputs are disabled (OE HIGH), or

a write operation is in progress (CE₁LOW and CE₂HIGH and

WE LOW). See the “Truth Table” on page 8 for a complete

description of read and write modes.

Logic Block Diagram

DATA IN DRIVERS

2M x 8

ARRAY

POWER

DOWN

COLUMN DECODER

Note

1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Cypress Semiconductor Corporation

Document #: 001-07721 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 07, 2007

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与CY62177DV30相关器件

型号	品牌	获取价格	描述	数据表
CY62177DV30_09	CYPRESS	获取价格	32-Mbit (2M x 16) Static RAM
CY62177DV30_11	CYPRESS	获取价格	32-Mbit (2M x 16) Static RAM
CY62177DV30_12	CYPRESS	获取价格	32-Mbit (2 M Ã 16) Static RAM
CY62177DV30L-55BAI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177DV30L-70BAI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177DV30LL	CYPRESS	获取价格	32-Mbit (2M x 16) Static RAM
CY62177DV30LL-55BAI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177DV30LL-55BAXI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177ESL-55ZXI	CYPRESS	获取价格	Standard SRAM, 2MX16, 55ns, CMOS, PDSO48, 12 X 18.40 MM, 1 MM HEIGHT, LEAD FREE, MO-142, T
CY62177ESL-55ZXIT	CYPRESS	获取价格	Standard SRAM, 2MX16, 55ns, CMOS, PDSO48,

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