Datasheet > CY62177DV20_08

CY62177DV20_08

更新时间： 2024-11-18 04:53:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	308K
描述
32-Mbit (2M x 16) Static RAM

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CY62177DV20_08 数据手册

CY62177DV20 MoBL2™

32-Mbit (2M x 16) Static RAM

by 99% when addresses are not toggling. The device can also

be put into standby mode when deselected (CE₁HIGH or CE₂

LOW or both BHE and BLE are HIGH). The input and output pins

(IO₀through IO₁₅) are placed in a high impedance state when:

the device is deselected (CE₁HIGH or CE₂LOW); outputs are

disabled (OE HIGH); both Byte High Enable and Byte Low

Enable are disabled (BHE, BLE HIGH); when a write operation

is in progress (CE₁LOW, CE₂HIGH and WE LOW).

Features

■ Very high speed: 70 ns

■ Wide voltage range: 1.7V – 2.2V

■ Ultra low active power

❐ Typical active current: 2 mA at f = 1 MHz

❐ Typical active current: 12 mA at f = f_MAX

To write to the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(BLE) is LOW, then data from IO pins (IO₀through IO₇) is written

into the location specified on the address pins (A₀through A₂₀).

If Byte High Enable (BHE) is LOW, then data from IO pins (IO₈

through IO₁₅) is written into the location specified on the address

pins (A₀through A₂₀).

■ Ultra low standby power

■ Easy memory expansion with CE₁, CE₂, and OE features

■ Automatic power down when deselected

■ CMOS for optimum speed and power

■ Offered in 48-ball VFBGA package

To read from the device, take Chip Enables (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins appears

on IO₀to IO₇. If Byte High Enable (BHE) is LOW, then data from

memory appears on IO₈to IO₁₅. See the Truth Table on page 9

for a complete description of read and write modes.

Functional Description

The CY62177DV20 is a high performance CMOS static RAM

organized as 2M words by 16 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^®) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that reduces power consumption

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

A ₄

2M × 16

RAM ARRAY

IO₀–IO₇

IO₈–IO₁₅

A ₃

A ₂

A ₁

A ₀

COLUMN DECODER

BHE

CE₂

PowerDown

Circuit

BHE

BLE

Cypress Semiconductor Corporation

Document #: 001-44018 Rev. **

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 08, 2008

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与CY62177DV20_08相关器件

型号	品牌	获取价格	描述	数据表
CY62177DV20LL-70BAI	CYPRESS	获取价格	32-Mbit (2M x 16) Static RAM
CY62177DV30	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177DV30_09	CYPRESS	获取价格	32-Mbit (2M x 16) Static RAM
CY62177DV30_11	CYPRESS	获取价格	32-Mbit (2M x 16) Static RAM
CY62177DV30_12	CYPRESS	获取价格	32-Mbit (2 M Ã 16) Static RAM
CY62177DV30L-55BAI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177DV30L-70BAI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177DV30LL	CYPRESS	获取价格	32-Mbit (2M x 16) Static RAM
CY62177DV30LL-55BAI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM
CY62177DV30LL-55BAXI	CYPRESS	获取价格	16-Mbit (2M x 8) Static RAM

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