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CY62168G30-45BVXI

更新时间： 2023-12-06 20:12:23
品牌 Logo 应用领域
英飞凌 - INFINEON 静态存储器
页数 文件大小 规格书
18页 434K
描述
Asynchronous SRAM

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CY62168G30-45BVXI 数据手册

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CY62168G30/CY62168GE30 MoBL  
16-Mbit (2M words × 8 bits) Static RAM  
with Error-Correcting Code (ECC)  
16-Mbit (2M words  
× 8 bits) Static RAM with Error-Correcting Code (ECC)  
Devices with a single chip enable input are accessed by  
asserting the chip enable input (CE) LOW. Dual chip enable  
devices are accessed by asserting both chip enable inputs – CE1  
as LOW and CE2 as HIGH.  
Features  
■ Ultra-low standby power  
❐ Typical standby current: 1.5 A  
❐ Maximum standby current: 8 A  
Write to the device by taking Chip Enable 1 (CE1) LOW and  
Chip Enable 2 (CE2) HIGH and the Write Enable (WE) input  
LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written  
■ High speed: 45 ns  
into the location specified on the address pins (A0 through A20).  
■ Embedded error-correcting code (ECC) for single-bit error  
correction  
Read from the device by taking Chip Enable 1 (CE1) and  
Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while  
forcing Write Enable (WE) HIGH. Under these conditions, the  
contents of the memory location specified by the address pins  
will appear on the I/O pins.  
■ Wide voltage range: 2.2 V to 3.6 V  
■ 1.0 V data retention  
■ Transistor-transistor logic (TTL) compatible inputs and outputs  
■ ERR pin to indicate 1-bit error detection and correction  
■ Available in Pb-free 48-ball VFBGA package  
The eight input and output pins (I/O0 through I/O7) are placed in  
a high impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a  
write operation is in progress (CE1 LOW and CE2 HIGH and WE  
LOW). See the Truth Table – CY62168G/CY62168GE on page  
13 for a complete description of read and write modes.  
Functional Description  
CY62168G30 and CY62168GE30 are high-performance CMOS  
low-power (MoBL) SRAM devices with embedded ECC. Both  
devices are offered in single and dual chip enable options and in  
multiple pin configurations. The CY62168GE30 device includes  
an error indication pin that signals a single-bit error-detection and  
correction event during a read cycle.  
On CY62168GE30 devices, the detection and correction of a  
single bit error in the accessed location is indicated by the  
assertion of the ERR output (ERR = HIGH)[1]  
.
The CY62168G30 and CY62168GE30 devices are available in  
a Pb-free 48-pin VFBGA package. The logic block diagrams are  
on page 2.  
Product Portfolio  
Power Dissipation  
Features and  
Options  
(see Pin  
Configurations  
section)  
Operating ICC, (mA)  
Speed  
Product  
Range  
VCC Range (V)  
Standby, ISB2 (µA)  
(ns)  
f = fmax  
Typ[2]  
Max  
Typ[2]  
Max  
CY62168G(E)30[3, 4] Single or dual Chip  
Enables  
Industrial  
2.2 V–3.6 V  
45  
29  
35  
1.5  
8
Optional ERR pin  
Notes  
1. This device does not support automatic write-back on error detection.  
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 3 V (for V range of 2.2 V–3.6 V), T = 25 °C.  
CC  
CC  
A
3. This device offers improved I , I  
and I  
specifications compared to the previous revision with same marketing part number.  
CC SB1  
SB2  
4. For previous version of this device, kindly referhere. Further details about improvement and comparison between old and new versions can be found in the PCN193805.  
Cypress Semiconductor Corporation  
Document Number: 002-28440 Rev. *A  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised March 20, 2020  
1234567...18

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