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CDC509PWR

更新时间： 2024-11-21 02:58:43
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
9页 134K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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中文翻译

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CDC509PWR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP-24针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.69Is Samacsys：N
系列：509输入调节：STANDARD
JESD-30 代码：R-PDSO-G24JESD-609代码：e4
长度：7.8 mm负载电容（CL）：30 pF
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.02 A
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：24
实输出次数：9最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP24,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.2 ns座面最大高度：1.2 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
最小 fmax：125 MHzBase Number Matches：1

CDC509PWR 数据手册

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CDC509  
3.3-V PHASE-LOCK LOOP CLOCK DRIVER  
SCAS576B – JULY 1996 – REVISED JANUARY 1998  
PW PACKAGE  
(TOP VIEW)  
Phase-Lock Loop Clock Distribution for  
Synchronous DRAM Applications  
Distributes One Clock Input to One Bank of  
Five and One Bank of Four Outputs  
AGND  
CLK  
AV  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
V
2
CC  
CC  
Separate Output Enable for Each Output  
Bank  
1Y0  
1Y1  
1Y2  
GND  
GND  
1Y3  
V
3
CC  
2Y0  
2Y1  
GND  
GND  
2Y2  
2Y3  
4
External Feedback (FBIN) Pin Is Used to  
Synchronize the Outputs to the Clock Input  
5
6
7
No External RC Network Required  
8
Operates at 3.3-V V  
CC  
1Y4  
9
Packaged in Plastic 24-Pin Thin Shrink  
Small-Outline Package  
V
10  
11  
12  
V
CC  
CC  
1G  
FBOUT  
2G  
FBIN  
description  
The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to  
precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It  
is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V V and is designed  
CC  
to drive up to five clock loads per output.  
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output  
signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can  
be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs  
switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low  
state.  
Unlike many products containing PLLs, the CDC509 does not require external RC networks. The loop filter for  
the PLL is included on-chip, minimizing component count, board space, and cost.  
Because it is based on PLL circuitry, the CDC509 requires a stabilization time to achieve phase lock of the  
feedback signal to the reference signal. This stabilization time is required, following power up and application  
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or  
feedback signals. The PLL can be bypassed for test purposes by strapping AV  
to ground.  
CC  
The CDC509 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
2G  
OUTPUTS  
2Y  
1Y  
(0:4)  
1G  
CLK  
FBOUT  
(0:3)  
X
L
X
L
L
H
H
H
H
L
L
L
L
L
H
H
H
H
L
H
L
L
H
H
H
H
H
L
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

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CDC509PWR 替代型号

型号 品牌 替代类型 描述 数据表
CDCVF2509PW TI

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 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF2509PWR TI

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 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCF2509PWR TI

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 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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