CDC536

更新时间： 2024-11-29 22:40:11

品牌	Logo	应用领域
德州仪器 - TI		时钟驱动器输出元件
页数	文件大小	规格书
12页	171K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

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CDC536 数据手册

CDC536

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

WITH 3-STATE OUTPUTS

SCAS378F – APRIL 1994 – REVISED OCTOBER 1998

DB OR DL PACKAGE

(TOP VIEW)

Low-Output Skew for Clock-Distribution

and Clock-Generation Applications

Operates at 3.3-V V

Distributes One Clock Input to Six Outputs

AGND

CLKIN

SEL

GND

1Y1

AGND

FBIN

TEST

CLR

One Select Input Configures Three Outputs

to Operate at One-Half or Double the Input

Frequency

No External RC Network Required

2Y1

GND

External Feedback Pin (FBIN) Is Used to

Synchronize the Outputs to the Clock Input

GND

Application for Synchronous DRAM,

High-Speed Microprocessor

1Y2 10

19 2Y2

GND

Negative-Edge-Triggered Clear for

Half-Frequency Outputs

GND

16 2Y3

1Y3 13

TTL-Compatible Inputs and Outputs

15 GND

Outputs Drive 50-Ω Parallel-Terminated

Transmission Lines

State-of-the-Art EPIC-ΙΙB BiCMOS Design

Significantly Reduces Power Dissipation

Distributed V

Switching Noise

and Ground Pins Reduce

Packaged in Plastic 28-Pin Shrink Small

Outline Package

description

TheCDC536isahigh-performance, low-skew, low-jitterclockdriver. Itusesaphase-lockloop(PLL)toprecisely

align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically

designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to

100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V

and is designed to drive a 50- transmission line.

The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock

(CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between

CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.

The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL)

input configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin

is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the

duty cycle at the input clock.

Output-enable(OE)isprovidedforoutputcontrol. WhenOEishigh, theoutputsareinthehigh-impedancestate.

When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass

the PLL. TEST should be strapped to GND for normal operation.

Unlike many products containing PLLs, the CDC536 does not require external RC networks. The loop filter for

the PLL is included on-chip, minimizing component count, board space, and cost.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...12

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与CDC536相关器件

型号	品牌	获取价格	描述	数据表
CDC536DB	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC536DBG4	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC536DBLE	ETC	获取价格	Six Distributed-Output Clock Driver
CDC536DBR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC536DBRG4	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC536DL	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC536DLR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC5801	TI	获取价格	LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT
CDC5801A	TI	获取价格	LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE AND PHASE ALIGNMENT
CDC5801ADBQ	TI	获取价格	LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY

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