Datasheet > CDC5806

CDC5806

更新时间： 2024-11-16 22:40:11

品牌	Logo	应用领域
德州仪器 - TI		时钟发生器电视
页数	文件大小	规格书
8页	110K
描述
THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS

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CDC5806 数据手册

CDC5806

www.ti.com

SCAS760A–MARCH 2004–REVISED JULY 2004

THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS

FEATURES

DESCRIPTION

•

High Performance Clock Generator

The CDC5806 is a clock generator which synthesizes

video clocks, audio clocks, CPU clock, ASIC clock,

USB clock, and a memory card clock from a 54-MHz

system clock.

Clock Input Compatible With LVCMOS/LVTTL

Requires a 54-MHz Input Clock to Generate

Multiple Output Frequencies

Three phase-locked loops (PLLs) are used to

generate the different frequencies from the system

clock. On-chip loop filters and internal feedback

eliminate the need for external components.

•

Low Jitter for Clock Distribution

Generates the Following Clocks:

– VIDCLK 74.175824 MHz/54 MHz

(Buffered)

Since the CDC5806 is based on PLL circuitry, it

requires a stabilization time to achieve phase-lock of

the PLLs. The PLL stabilization time begins after the

reference clock input has a stable phase and

frequency.

– AUDCLK 16.9344 MHz/12.288 MHz

– CPUCLK 64 MHz

– ASICCLK 32 MHz

– USBCLK 48 MHz

The device operates from a single 3.3-V supply

voltage. The CDC5806 device is characterized for

operation from -40°C to 85°C.

– MCCLK 38.4 MHz/19.2 MHz/12 MHz

Operates From Single 3.3-V Supply

•

Low Peak-to-Peak Period Jitter (150 ps

Max)

PW PACKAGE

(TOP VIEW)

•

PLLs Are Powered Down, if No Valid REF_IN

Clock (< 5 MHz) is Detected or the

V_DDis Below 2 V

VIDSEL

REF_IN

PLL1VDD

VIDCLK

PLL1VSS

PLL2VDD

AUDCLK

PLL2VSS

AUDSEL

MCSEL

ASICCLK

PLL3VDD

PLL3VSS

CPUCLK

PLL3VDD

PLL3VSS

USBCLK

PLL3VDD

PLL3VSS

MCCLK

•

PLL Loop Filter Components Integrated

Packaged in TSSOP (PW) 20-Pin Package

Industrial Temperature Range -40°C to

85°C Applications

APPLICATIONS

•

Digital Television With a Memory Card

Interface

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7 8

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与CDC5806相关器件

型号	品牌	获取价格	描述	数据表
CDC5806PWG4	TI	获取价格	6 Output PLL Frequency Generator 20-TSSOP -40 to 85
CDC582	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS
CDC582PAH	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS
CDC586	TI	获取价格	3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC586PAH	TI	获取价格	3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC586PAHR	TI	获取价格	3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 52-TQFP
CDC586PAHRG4	TI	获取价格	3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 52-TQFP
CDC586PBG	ETC	获取价格	Twelve Distributed-Output Clock Driver
CDC587DGGR	TI	获取价格	CDC SERIES, PLL BASED CLOCK DRIVER, 16 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO56
CDC5D20	SUMIDA	获取价格	CDC5D20

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