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CDC5806PWG4 PDF预览

CDC5806PWG4

更新时间： 2024-11-17 21:01:35
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
12页 345K
描述
6 Output PLL Frequency Generator 20-TSSOP -40 to 85

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中文翻译

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CDC5806PWG4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP20,.25
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.82
系列：5806输入调节：STANDARD
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：6.5 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：20
实输出次数：6最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TUBE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

CDC5806PWG4 数据手册

 浏览型号CDC5806PWG4的Datasheet PDF文件第2页浏览型号CDC5806PWG4的Datasheet PDF文件第3页浏览型号CDC5806PWG4的Datasheet PDF文件第4页浏览型号CDC5806PWG4的Datasheet PDF文件第5页浏览型号CDC5806PWG4的Datasheet PDF文件第6页浏览型号CDC5806PWG4的Datasheet PDF文件第7页 
CDC5806  
www.ti.com  
SCAS760A–MARCH 2004–REVISED JULY 2004  
THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS  
FEATURES  
DESCRIPTION  
•
•
•
High Performance Clock Generator  
The CDC5806 is a clock generator which synthesizes  
video clocks, audio clocks, CPU clock, ASIC clock,  
USB clock, and a memory card clock from a 54-MHz  
system clock.  
Clock Input Compatible With LVCMOS/LVTTL  
Requires a 54-MHz Input Clock to Generate  
Multiple Output Frequencies  
Three phase-locked loops (PLLs) are used to  
generate the different frequencies from the system  
clock. On-chip loop filters and internal feedback  
eliminate the need for external components.  
•
•
Low Jitter for Clock Distribution  
Generates the Following Clocks:  
– VIDCLK 74.175824 MHz/54 MHz  
(Buffered)  
Since the CDC5806 is based on PLL circuitry, it  
requires a stabilization time to achieve phase-lock of  
the PLLs. The PLL stabilization time begins after the  
reference clock input has a stable phase and  
frequency.  
– AUDCLK 16.9344 MHz/12.288 MHz  
– CPUCLK 64 MHz  
– ASICCLK 32 MHz  
– USBCLK 48 MHz  
The device operates from a single 3.3-V supply  
voltage. The CDC5806 device is characterized for  
operation from -40°C to 85°C.  
– MCCLK 38.4 MHz/19.2 MHz/12 MHz  
Operates From Single 3.3-V Supply  
•
•
Low Peak-to-Peak Period Jitter (150 ps  
Max)  
PW PACKAGE  
(TOP VIEW)  
•
PLLs Are Powered Down, if No Valid REF_IN  
Clock (< 5 MHz) is Detected or the  
VDD is Below 2 V  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VIDSEL  
REF_IN  
PLL1VDD  
VIDCLK  
PLL1VSS  
PLL2VDD  
AUDCLK  
PLL2VSS  
AUDSEL  
MCSEL  
ASICCLK  
PLL3VDD  
PLL3VSS  
CPUCLK  
PLL3VDD  
PLL3VSS  
USBCLK  
PLL3VDD  
PLL3VSS  
MCCLK  
•
•
•
PLL Loop Filter Components Integrated  
Packaged in TSSOP (PW) 20-Pin Package  
Industrial Temperature Range -40°C to  
85°C Applications  
APPLICATIONS  
•
Digital Television With a Memory Card  
Interface  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004, Texas Instruments Incorporated  
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