CDC5801

更新时间： 2024-11-16 22:40:11

品牌	Logo	应用领域
德州仪器 - TI		时钟
页数	文件大小	规格书
16页	215K
描述
LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CDC5801 数据手册

CDC5801

LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH

PROGRAMMABLE DELAY AND PHASE ALIGNMENT

SCAS682A – OCTOBER 2002

Low Jitter Clock Multiplier by x4, x6, x8.

Input Frequency Range (19 MHz to

125 MHz). Supports Output Frequency

From 150 MHz to 500 MHz

Applications: Video Graphics, Gaming

Products, Datacom, Telecom

Accepts LVCMOS, LVTTL Inputs for

REFCLK Terminal

Low Jitter Clock Divider by /2, /3, /4. Input

Frequency Range (50 MHz to 125 MHz).

Supports Ranges of Output Frequency

From 12.5 MHz to 62.5 MHz

Accepts Other Single-Ended Signal Levels

at REFCLK Terminal by Programming

Proper V REF Voltage Level (For

Example, HSTL 1.5 if V REF = 1.6 V)

2.6 mUI Programmable Bidirectional Delay

Steps

Supports Industrial Temperature Range of

–40 C to 85 C

Typical 8.0-ps Phase Jitter (12 kHz to

20 MHz) @ 500 MHz

DBQ PACKAGE

(TOP VIEW)

Typical 2.1-ps RMS Period Jitter (Entire

Frequency Band) @ 500 MHz

REF

One Single-Ended Input and One

Differential Output Pair

REFCLK

GNDP

GND

GNDO

CLKOUT

Output Can Drive LVPECL, LVDS, and

LVTTL

LEADLAG

DLYCTRL

GNDPA

Three Power Operating Modes to Minimize

Power

CLKOUTB

GNDO

Low Power Consumption (Typical 200 mW

at 500 MHz)

MULT0/DIV0

MULT1/DIV1

Packaged in a Shrink Small-Outline

Package (DBQ)

STOPB

PWRDNB 12

13 P2

No External Components Required for PLL

NC – No internal connection

Spread Spectrum Clock Tracking Ability to

Reduce EMI

description

The CDC5801 device provides clock multiplication and division from a single-ended reference clock (REFCLK)

to a differential output pair (CLKOUT/CLKOUTB). The multiply and divide terminals (MULT/DIV0:1) provide

selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies ranging

from 12.5 MHz to 500 MHz with a clock input reference (REFCLK) ranging from 19 MHz to 125 MHz. Please

see Table 1 and Table 2 for detail frequency support.

The implemented phase aligner provides the possibility to phase align (zero delay) between

CLKOUT/CLKOUTB and REFCLK or any other CLK in the system by feeding the clocks that need to be aligned

to the DLYCTRL and the LEADLAG terminals.

The phase aligner also allows the user to delay or advance the CLKOUT/CLKOUTB with steps of 2.6 mUI (unit

interval). For every rising edge on the DLYCTRL terminal the output clocks are delayed by 2.6-mUI step size

as long as there is low on the LEADLAG terminal. Similarly for every rising edge on the DLYCTRL terminal the

output clocks are advanced by 2.6-mUI step size as long as there is high on the LEADLAG terminal. As the

phase between REFCLK and CLKOUT/CLKOUTB is random after power up, the application may implement

a self calibration routine at power up to produce a certain phase start position, before programming a fixed delay

with the clock on the DLYCTRL terminal.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...16

中文翻译

下载PDF

与CDC5801相关器件

型号	品牌	获取价格	描述	数据表
CDC5801A	TI	获取价格	LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE AND PHASE ALIGNMENT
CDC5801ADBQ	TI	获取价格	LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY
CDC5801ADBQG4	TI	获取价格	Low Jitter Clock Multiplier & Divider w/Programmable Delay & Phase Alignme
CDC5801ADBQR	TI	获取价格	LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY
CDC5806	TI	获取价格	THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS
CDC5806PWG4	TI	获取价格	6 Output PLL Frequency Generator 20-TSSOP -40 to 85
CDC582	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS
CDC582PAH	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS
CDC586	TI	获取价格	3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC586PAH	TI	获取价格	3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

与CDC5801相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

17
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

12
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

42
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

34

产品中心

服务支持

精选活动

关于我们

帮助中心

CDC5801

CDC5801 数据手册

与CDC5801相关器件

与CDC5801相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CDC5801

CDC5801 数据手册

与CDC5801相关器件

与CDC5801相关文章

您还可以找

您在本页遇到什么问题？