CDC5801ADBQR

更新时间： 2024-11-17 12:54:03

品牌	Logo	应用领域
德州仪器 - TI		时钟
页数	文件大小	规格书
18页	626K
描述
LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY

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CDC5801ADBQR 数据手册

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SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005

Low Jitter Clock Multiplier by x4, x6, x8.

Input Frequency Range (19 MHz to

125 MHz). Supports Output Frequency

From 150 MHz to 500 MHz

Applications: Video Graphics, Gaming

Products, Datacom, Telecom

Accepts LVCMOS, LVTTL Inputs for

REFCLK Terminal

Fail-Safe Power Up Initialization

Accepts Other Single-Ended Signal Levels

at REFCLK Terminal by Programming

Low Jitter Clock Divider by /2, /3, /4. Input

Frequency Range (50 MHz to 125 MHz).

Supports Ranges of Output Frequency

From 12.5 MHz to 62.5 MHz

Proper V REF Voltage Level (For

Example, HSTL 1.5 if V REF = 1.6 V)

Supports Industrial Temperature Range of

−40 C to 85 C

2.6 mUI Programmable Bidirectional Delay

Steps

DBQ PACKAGE

(TOP VIEW)

Typical 8-ps Phase Jitter (12 kHz to 20 MHz)

at 500 MHz

Typical 2.1-ps RMS Period Jitter (Entire

Frequency Band) at 500 MHz

REF

REFCLK

One Single-Ended Input and One

Differential Output Pair

GNDP

GND

GNDO

CLKOUT

Output Can Drive LVPECL, LVDS, and

LVTTL

LEADLAG

DLYCTRL

GNDPA

CLKOUTB

GNDO

Three Power Operating Modes to Minimize

Power

Low Power Consumption (Typical 200 mW

at 500 MHz)

MULT0/DIV0

MULT1/DIV1

STOPB

Packaged in a Shrink Small-Outline

Package (DBQ)

PWRDNB 12

13 P2

NC − No internal connection

No External Components Required for PLL

Spread Spectrum Clock Tracking Ability to

Reduce EMI

description

The CDC5801A device provides clock multiplication and division from a single-ended reference clock

(REFCLK) to a differential output pair (CLKOUT/CLKOUTB). The multiply and divide terminals (MULT/DIV0:1)

provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies

ranging from 12.5 MHz to 500 MHz with a clock input reference (REFCLK) ranging from 19 MHz to 125 MHz.

See Table 1 and Table 2 for detail frequency support.

The implemented phase aligner provides the possibility to phase align (zero delay) between

CLKOUT/CLKOUTB and REFCLK or any other CLK in the system by feeding the clocks that need to be aligned

to the DLYCTRL and the LEADLAG terminals.

The phase aligner also allows the user to delay or advance the CLKOUT/CLKOUTB with steps of 2.6 mUI (unit

interval). For every rising edge on the DLYCTRL terminal, the output clocks are delayed by 2.6-mUI step size

as long as there is low on the LEADLAG terminal. Similarly, for every rising edge on the DLYCTRL terminal, the

output clocks are advanced by 2.6-mUI step size as long as there is high on the LEADLAG terminal. The

CDC5801A has a fail-safe power up initialization state-machine which supports proper operation under all

power up conditions. As the phase between REFCLK and CLKOUT/CLKOUTB is random after power up, the

application may implement a self calibration routine at power up to produce a certain phase start position, before

programming a fixed delay with the clock on the DLYCTRL terminal.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...18

中文翻译

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CDC5801ADBQR 替代型号

型号	品牌	替代类型	描述	数据表
CDC5801ADBQ	TI	完全替代	LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY

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