5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 时钟驱动器> CDC536DBR
CDC536DBR PDF预览

CDC536DBR

更新时间： 2024-11-17 12:36:19
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
14页 295K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

CDC536DBR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP, SSOP28,.3针数：28
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：1.6Is Samacsys：N
系列：536输入调节：STANDARD
JESD-30 代码：R-PDSO-G28JESD-609代码：e4
长度：10.2 mm负载电容（CL）：30 pF
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.032 A
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：28
实输出次数：6最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP28,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.5 ns
座面最大高度：2 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5.3 mm
最小 fmax：100 MHzBase Number Matches：1

CDC536DBR 数据手册

 浏览型号CDC536DBR的Datasheet PDF文件第2页浏览型号CDC536DBR的Datasheet PDF文件第3页浏览型号CDC536DBR的Datasheet PDF文件第4页浏览型号CDC536DBR的Datasheet PDF文件第5页浏览型号CDC536DBR的Datasheet PDF文件第6页浏览型号CDC536DBR的Datasheet PDF文件第7页 
CDC536  
www.ti.com  
SCAS378G–APRIL 1994–REVISED JULY 2004  
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS  
FEATURES  
DB OR DL PACKAGE  
(TOP VIEW)  
•
Low-Output Skew for Clock-Distribution and  
Clock-Generation Applications  
•
•
•
Operates at 3.3-V VCC  
AV  
AV  
CC  
1
2
3
4
5
6
7
8
9
28  
27  
CC  
AGND  
CLKIN  
SEL  
OE  
GND  
1Y1  
AGND  
Distributes One Clock Input to Six Outputs  
26 FBIN  
One Select Input Configures Three Outputs to  
Operate at One-Half or Double the Input  
Frequency  
TEST  
CLR  
25  
24  
23  
22  
V
CC  
•
•
No External RC Network Required  
2Y1  
External Feedback Pin (FBIN) Is Used to  
Synchronize the Outputs to the Clock Input  
V
CC  
21 GND  
20  
19 2Y2  
GND  
1Y2 10  
V
CC  
•
•
Application for Synchronous DRAM,  
High-Speed Microprocessor  
V
CC  
GND  
11  
12  
13  
14  
18  
17  
16  
GND  
1Y3  
V
CC  
Negative-Edge-Triggered Clear for  
Half-Frequency Outputs  
2Y3  
V
CC  
15 GND  
•
•
TTL-Compatible Inputs and Outputs  
Outputs Drive 50-Ω Parallel-Terminated  
Transmission Lines  
•
•
•
State-of-the-Art EPIC-IIB™ BiCMOS Design  
Significantly Reduces Power Dissipation  
Distributed VCC and Ground Pins Reduce  
Switching Noise  
Packaged in Plastic 28-Pin Shrink Small  
Outline Package  
DESCRIPTION  
The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely  
align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically  
designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to  
100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V  
VCC and is designed to drive a 50-W transmission line.  
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock  
(CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between  
CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.  
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input  
configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed  
back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty  
cycle at the input clock.  
Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state.  
When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass  
the PLL. TEST should be strapped to GND for normal operation.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-IIB is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1994–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...14

中文翻译

下载PDF

CDC536DBR 替代型号

型号 品牌 替代类型 描述 数据表
CDC536DBRG4 TI

完全替代

 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC536DBG4 TI

完全替代

 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC536DB TI

完全替代

 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

与CDC536DBR相关器件

型号 品牌 获取价格 描述 数据表
CDC536DBRG4 TI

获取价格

 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC536DL TI

获取价格

 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC536DLR TI

获取价格

 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC5801 TI

获取价格

 		LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT
CDC5801A TI

获取价格

 		LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE AND PHASE ALIGNMENT
CDC5801ADBQ TI

获取价格

 		LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY
CDC5801ADBQG4 TI

获取价格

 		Low Jitter Clock Multiplier & Divider w/Programmable Delay & Phase Alignme
CDC5801ADBQR TI

获取价格

 		LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY
CDC5806 TI

获取价格

 		THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS
CDC5806PWG4 TI

获取价格

 		6 Output PLL Frequency Generator 20-TSSOP -40 to 85

与CDC536DBR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证