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CDC536DBRG4 PDF预览

CDC536DBRG4

更新时间： 2024-11-17 12:36:19
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器输出元件
页数 文件大小 规格书
14页 295K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

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中文翻译

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CDC536DBRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP, SSOP28,.3针数：28
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：12 weeks风险等级：5.24
系列：536输入调节：STANDARD
JESD-30 代码：R-PDSO-G28JESD-609代码：e4
长度：10.2 mm负载电容（CL）：30 pF
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.032 A
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：28
实输出次数：6最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP28,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.5 ns
座面最大高度：2 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5.3 mm
最小 fmax：100 MHzBase Number Matches：1

CDC536DBRG4 数据手册

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CDC536  
www.ti.com  
SCAS378G–APRIL 1994–REVISED JULY 2004  
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS  
FEATURES  
DB OR DL PACKAGE  
(TOP VIEW)  
•
Low-Output Skew for Clock-Distribution and  
Clock-Generation Applications  
•
•
•
Operates at 3.3-V VCC  
AV  
AV  
CC  
1
2
3
4
5
6
7
8
9
28  
27  
CC  
AGND  
CLKIN  
SEL  
OE  
GND  
1Y1  
AGND  
Distributes One Clock Input to Six Outputs  
26 FBIN  
One Select Input Configures Three Outputs to  
Operate at One-Half or Double the Input  
Frequency  
TEST  
CLR  
25  
24  
23  
22  
V
CC  
•
•
No External RC Network Required  
2Y1  
External Feedback Pin (FBIN) Is Used to  
Synchronize the Outputs to the Clock Input  
V
CC  
21 GND  
20  
19 2Y2  
GND  
1Y2 10  
V
CC  
•
•
Application for Synchronous DRAM,  
High-Speed Microprocessor  
V
CC  
GND  
11  
12  
13  
14  
18  
17  
16  
GND  
1Y3  
V
CC  
Negative-Edge-Triggered Clear for  
Half-Frequency Outputs  
2Y3  
V
CC  
15 GND  
•
•
TTL-Compatible Inputs and Outputs  
Outputs Drive 50-Ω Parallel-Terminated  
Transmission Lines  
•
•
•
State-of-the-Art EPIC-IIB™ BiCMOS Design  
Significantly Reduces Power Dissipation  
Distributed VCC and Ground Pins Reduce  
Switching Noise  
Packaged in Plastic 28-Pin Shrink Small  
Outline Package  
DESCRIPTION  
The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely  
align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically  
designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to  
100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V  
VCC and is designed to drive a 50-W transmission line.  
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock  
(CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between  
CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.  
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input  
configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed  
back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty  
cycle at the input clock.  
Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state.  
When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass  
the PLL. TEST should be strapped to GND for normal operation.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-IIB is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1994–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...14

中文翻译

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CDC536DBRG4 替代型号

型号 品牌 替代类型 描述 数据表
CDC536DBR TI

完全替代

 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC536DBG4 TI

完全替代

 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC536DB TI

完全替代

 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

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