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CDCVF2509PW PDF预览

CDCVF2509PW

更新时间： 2024-10-01 22:28:55
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 146K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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中文翻译

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CDCVF2509PW 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP-24针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.33.00.01Factory Lead Time：1 week
风险等级：1.64Is Samacsys：N
系列：2509输入调节：STANDARD
JESD-30 代码：R-PDSO-G24JESD-609代码：e4
长度：7.8 mm负载电容（CL）：25 pF
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.012 A
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：24
实输出次数：9最高工作温度：85 °C
最低工作温度：输出特性：3-STATE WITH SERIES RESISTOR
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP24,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TUBE
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：3.9 ns传播延迟（tpd）：3.9 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.1 ns
座面最大高度：1.2 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：OTHER端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mm最小 fmax：175 MHz
Base Number Matches：1

CDCVF2509PW 数据手册

 浏览型号CDCVF2509PW的Datasheet PDF文件第2页浏览型号CDCVF2509PW的Datasheet PDF文件第3页浏览型号CDCVF2509PW的Datasheet PDF文件第4页浏览型号CDCVF2509PW的Datasheet PDF文件第5页浏览型号CDCVF2509PW的Datasheet PDF文件第6页浏览型号CDCVF2509PW的Datasheet PDF文件第7页 
CDCVF2509  
3.3-V PHASE-LOCK LOOP CLOCK DRIVER  
SCAS637 – DECEMBER 1999  
PW PACKAGE  
(TOP VIEW)  
Designed to Meet and Exceed PC133  
SDRAM Registered DIMM Specification  
Rev. 1.1  
AGND  
CLK  
AV  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Spread Spectrum Clock Compatible  
V
2
CC  
CC  
Operating Frequency 50 MHz to 175 MHz  
1Y0  
1Y1  
1Y2  
GND  
GND  
1Y3  
V
3
CC  
Static Phase Error Distribution at 66MHz to  
166 MHz is ±125 ps  
2Y0  
2Y1  
GND  
GND  
2Y2  
2Y3  
4
5
6
Jitter (cyc – cyc) at 66 MHz to 166 MHz is  
|70| ps  
7
8
Advanced Deep Sub-Micron Process  
Results in More Than 40% Lower Power  
Consumption Versus Current Generation  
PC133 Devices  
1Y4  
9
V
10  
11  
12  
V
CC  
CC  
1G  
FBOUT  
2G  
FBIN  
Available in Plastic 24-Pin TSSOP  
Phase-Lock Loop Clock Distribution for  
Synchronous DRAM Applications  
Distributes One Clock Input to One Bank of  
Five and One Bank of Four Outputs  
Separate Output Enable for Each Output  
Bank  
External Feedback (FBIN) Terminal Is Used  
to Synchronize the Outputs to the Clock  
Input  
25-Ω On-Chip Series Damping Resistors  
No External RC Network Required  
Operates at 3.3 V  
description  
The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL  
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.  
It is specifically designed for use with synchronous DRAMs. The CDCVF2509 operates at 3.3 V V . It also  
CC  
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.  
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output  
signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled  
or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in  
phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.  
Unlike many products containing PLLs, the CDCVF2509 does not require external RC networks. The loop filter  
for the PLL is included on-chip, minimizing component count, board space, and cost.  
Because it is based on PLL circuitry, the CDCVF2509 requires a stabilization time to achieve phase lock of the  
feedback signal to the reference signal. This stabilization time is required, following power up and application  
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback  
signals. The PLL can be bypassed for test purposes by strapping AV  
to ground.  
CC  
The CDCVF2509 is characterized for operation from 0°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

中文翻译

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CDCVF2509PW 替代型号

型号 品牌 替代类型 描述 数据表
CDCVF2509APWR TI

完全替代

 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2509APW TI

完全替代

 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2509PWR TI

完全替代

 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

与CDCVF2509PW相关器件

型号 品牌 获取价格 描述 数据表
CDCVF2509PWR TI

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 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF2510 TI

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 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF2510A TI

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 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2510APW TI

获取价格

 		3.3-V Phase-Lock Loop Clock Driver with Power Down Mode 24-TSSOP 0 to 85
CDCVF2510APWR TI

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 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2510APWRG4 TI

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 		3.3-V Phase-Lock Loop Clock Driver with Power Down Mode 24-TSSOP 0 to 85
CDCVF2510PW TI

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 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF2510PWLE TI

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 		暂无描述
CDCVF2510PWR TI

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 		适用于 DRAM 应用且具有 10 个输出的 3.3V 锁相环路时钟驱动器 | PW |
CDCVF2510PWRG4 TI

获取价格

 		3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 0 to 85

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