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CDC516DGG PDF预览

CDC516DGG

更新时间： 2024-11-16 22:40:11
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 161K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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中文翻译

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CDC516DGG 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP48,.3,20针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.98Is Samacsys：N
系列：516输入调节：STANDARD
JESD-30 代码：R-PDSO-G48JESD-609代码：e4
长度：12.5 mm负载电容（CL）：30 pF
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.02 A
湿度敏感等级：2功能数量：1
反相输出次数：端子数量：48
实输出次数：16最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TUBE峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：0.02 mA
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.2 ns
座面最大高度：1.2 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mm最小 fmax：125 MHz
Base Number Matches：1

CDC516DGG 数据手册

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CDC516  
3.3-V PHASE-LOCK LOOP CLOCK DRIVER  
SCAS575A – JULY 1996 – REVISED JANUARY 1998  
DGG PACKAGE  
(TOP VIEW)  
Phase-Lock Loop Clock Distribution for  
Synchronous DRAM Applications  
Distributes One Clock Input to Four Banks  
of Four Outputs  
V
1Y0  
1Y1  
GND  
GND  
1Y2  
1Y3  
V
V
CC  
1
2
3
4
5
6
7
8
9
48  
47  
46  
45  
44  
43  
42  
41  
40  
CC  
4Y0  
4Y1  
GND  
GND  
4Y2  
4Y3  
Separate Output Enable for Each Output  
Bank  
External Feedback Pin (FBIN) Is Used to  
Synchronize the Outputs to the Clock Input  
No External RC Network Required  
V
Operates at 3.3-V V  
CC  
Packaged in Plastic 48-Pin Thin Shrink  
Small-Outline Package  
CC  
CC  
1G  
4G  
GND 10  
AV  
39 GND  
AV  
11  
12  
38  
37  
CC  
CC  
CLK  
FBIN  
description  
AGND 13  
AGND 14  
GND 15  
2G 16  
36 AGND  
35 FBOUT  
34 GND  
33 3G  
The CDC516 is a high-performance, low-skew,  
low-jitter, phase-lock loop clock driver. It uses a  
phase-lock loop (PLL) to precisely align, in both  
frequency and phase, the feedback output  
(FBOUT) to the clock (CLK) input signal. It is  
specifically designed for use with synchronous  
V
17  
32  
V
CC  
CC  
2Y0 18  
2Y1 19  
GND 20  
GND 21  
2Y2 22  
2Y3 23  
31 3Y0  
30 3Y1  
29 GND  
28 GND  
27 3Y2  
26 3Y3  
DRAMs. The CDC516 operates at 3.3-V V  
and  
CC  
is designed to drive up to five clock loads per  
output.  
Four banks of four outputs provide 16 low-skew,  
low-jitter copies of the input clock. Output signal  
duty cycles are adjusted to 50 percent,  
independent of the duty cycle at the input clock.  
Each bank of outputs can be enabled or disabled  
separately via the 1G, 2G, 3G, and 4G control  
inputs. When the G inputs are high, the outputs  
switchinphaseandfrequencywithCLK;whenthe  
G inputs are low, the outputs are disabled to the  
logic-low state.  
V
24  
25  
V
CC  
CC  
Unlike many products containing PLLs, the CDC516 does not require external RC networks. The loop filter for  
the PLL is included on-chip, minimizing component count, board space, and cost.  
Because it is based on PLL circuitry, the CDC516 requires a stabilization time to achieve phase lock of the  
feedback signal to the reference signal. This stabilization time is required following power up and application  
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or  
feedback signals. The PLL may be bypassed for test purposes by strapping AV  
to ground.  
CC  
The CDC516 is characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

中文翻译

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CDC516DGG 替代型号

型号 品牌 替代类型 描述 数据表
CDC516DGGG4 TI

完全替代

 具有三态输出的 3.3V 相位锁定环路时钟驱动器 | DGG | 48 | 0 to 70
CDC516DGGR TI

类似代替

 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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CDC516DGGG4 TI

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CDC516DGGR TI

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 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC536 TI

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CDC536DBLE ETC

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CDC536DBR TI

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 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC536DBRG4 TI

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 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC536DL TI

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 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC536DLR TI

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 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

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