CDCF2509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS624A – APRIL 1999 REVISED MAY 1999
PW PACKAGE
(TOP VIEW)
Designed to Meet PC133 SDRAM
Registered DIMM Specification Rev. 0.9
Spread Spectrum Clock Compatible
AGND
CLK
AV
1
24
23
22
21
20
19
18
17
16
15
14
13
Operating Frequency 25 MHz to 140 MHz
V
2
CC
CC
Static tPhase Error Distribution at 66MHz to
133 MHz is ±125 ps
1Y0
1Y1
1Y2
GND
GND
1Y3
V
3
CC
2Y0
2Y1
GND
GND
2Y2
2Y3
4
5
Jitter (cyc – cyc) at 66 MHz to 133 MHz is
|70| ps
6
7
Available in Plastic 24-Pin TSSOP
8
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
1Y4
9
V
10
11
12
V
CC
CC
Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs
1G
FBOUT
2G
FBIN
Separate Output Enable for Each Output
Bank
External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input
On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V
description
The CDCF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDCF2509 operates at 3.3 V V . It also
CC
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output
signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled
or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in
phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDCF2509 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDCF2509 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AV
to ground.
CC
The CDCF2509 is characterized for operation from 0°C to 85°C.
For application information refer to application reports High Speed Distribution Design Techniques for
CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread
Spectrum Clocking (SSC) (literature number SCAA039).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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