CDCF5801

更新时间： 2024-11-15 22:31:31

品牌	Logo	应用领域
德州仪器 - TI		时钟
页数	文件大小	规格书
17页	247K
描述
CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT

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CDCF5801 数据手册

CDCF5801

www.ti.com

SCAS698D–SEPTEMBER 2003–REVISED DECEMBER 2004

CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT

FEATURES

APPLICATIONS

•

Video Graphics

Gaming Products

Datacom

•

Low-Jitter Clock Multiplier: ×1, ×2, ×4, ×8

•

Programmable Bidirectional Delay Steps of

1.3 mUI

Telecom

•

Output Frequency Range of 25 MHz to

280 MHz

Noise Cancellation Created by FPGAs

Input Frequency Range of 12.5 MHz to

240 MHz

DBQ PACKAGE

(TOP VIEW)

•

Low Jitter Generation

VDDREF

REFCLK

VDDP

Single-Ended REFCLK Input With Adjustable

Trigger Level (Works With LVTTL, HSTL, and

LVPECL)

VDDO

GNDO

CLKOUT

CLKOUTB

GNDO

VDDO

MULT0

MULT1

GNDP

GND

•

Differential/Single-Ended Output

LEADLAG

DLYCTRL

GNDPA

VDDPA

VDDPD

STOPB

PWRDNB

Output Can Drive LVPECL, LVDS, and LVTTL

Three Power Operating Modes to Minimize

Power

•

Low Power Consumption (< 190 mW at

280 MHz/3.3 V)

Packaged in a Shrink Small-Outline Package

(DBQ)

•

No External Components Required for PLL

Spread Spectrum Clock Tracking Ability to

Reduce EMI (SSC)

DESCRIPTION

The CDCF5801 provides clock multiplication from a reference clock (REFCLK) signal with the unique capability

to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3 mUI through a phase aligner. For every rising

edge on the DLYCTRL pin the CLKOUT is delayed by a 1.3-mUI step size as long as the LEADLAG input

detects a low signal at the time of the DLYCTRL rising edge. Similarly for every rising edge on the DLYCTRL pin

the CLKOUT is advanced by a 1.3-mUI step size as long as the LEADLAG pin is high during the transition. This

unique capability allows the device to phase align (zero delay) between CLKOUT/CLKOUTB and any one other

CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG pins. Also it

provides the capability to program a fixed delay by providing the proper number of edges on the DLYCTRL pin,

while strapping the LEADLAG pin to dc high or low. Further possible applications are:

•

Aligning the rising edge of the output clock signal to the input clock rising edge

Avoiding PLL instability in applications that require very long PLL feedback lines

Isolation of jitter and digital switching noise

Limitation of jitter in systems with good ppm frequency stability

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...17

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CDCF5801 替代型号

型号	品牌	替代类型	描述	数据表
CDCF5801A	TI	功能相似	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT

与CDCF5801相关器件

型号	品牌	获取价格	描述	数据表
CDCF5801_14	TI	获取价格	CLOCK MULTIPLIER
CDCF5801A	TI	获取价格	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
CDCF5801ADBQ	TI	获取价格	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
CDCF5801ADBQG4	TI	获取价格	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
CDCF5801ADBQR	TI	获取价格	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
CDCF5801ADBQRG4	TI	获取价格	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
CDCF5801DBQ	TI	获取价格	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
CDCF5801DBQG4	TI	获取价格	Low Jitter PLL Based Multiplier/Divider with programmable delay lines down to sub 10ps 24-
CDCF5801DBQR	TI	获取价格	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
CDCF5801DBQRG4	TI	获取价格	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT

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