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CDCF5801DBQ PDF预览

CDCF5801DBQ

更新时间： 2024-09-28 21:57:59
品牌 Logo 应用领域
德州仪器 - TI 时钟
页数 文件大小 规格书
17页 247K
描述
CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT

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中文翻译

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CDCF5801DBQ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Not Recommended零件包装代码：SOIC
包装说明：SSOP, SSOP24,.24针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.21
其他特性：DIFFERENTIAL/SINGLE-ENDED OUTPUT AVAILABLE系列：5801
输入调节：STANDARDJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：8.65 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.016 A
湿度敏感等级：2功能数量：1
反相输出次数：端子数量：24
实输出次数：1最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP24,.24封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TUBE
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：75 mA认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm
最小 fmax：280 MHzBase Number Matches：1

CDCF5801DBQ 数据手册

 浏览型号CDCF5801DBQ的Datasheet PDF文件第2页浏览型号CDCF5801DBQ的Datasheet PDF文件第3页浏览型号CDCF5801DBQ的Datasheet PDF文件第4页浏览型号CDCF5801DBQ的Datasheet PDF文件第5页浏览型号CDCF5801DBQ的Datasheet PDF文件第6页浏览型号CDCF5801DBQ的Datasheet PDF文件第7页 
CDCF5801  
www.ti.com  
SCAS698D–SEPTEMBER 2003–REVISED DECEMBER 2004  
CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT  
FEATURES  
APPLICATIONS  
•
•
•
•
•
Video Graphics  
Gaming Products  
Datacom  
•
Low-Jitter Clock Multiplier: ×1, ×2, ×4, ×8  
•
Programmable Bidirectional Delay Steps of  
1.3 mUI  
Telecom  
•
•
Output Frequency Range of 25 MHz to  
280 MHz  
Noise Cancellation Created by FPGAs  
Input Frequency Range of 12.5 MHz to  
240 MHz  
DBQ PACKAGE  
(TOP VIEW)  
•
•
Low Jitter Generation  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VDDREF  
REFCLK  
VDDP  
P0  
P1  
Single-Ended REFCLK Input With Adjustable  
Trigger Level (Works With LVTTL, HSTL, and  
LVPECL)  
2
3
VDDO  
GNDO  
CLKOUT  
NC  
CLKOUTB  
GNDO  
VDDO  
MULT0  
MULT1  
P2  
4
GNDP  
GND  
5
•
•
•
Differential/Single-Ended Output  
6
LEADLAG  
DLYCTRL  
GNDPA  
VDDPA  
VDDPD  
STOPB  
PWRDNB  
Output Can Drive LVPECL, LVDS, and LVTTL  
7
Three Power Operating Modes to Minimize  
Power  
8
9
•
•
Low Power Consumption (< 190 mW at  
280 MHz/3.3 V)  
10  
11  
12  
Packaged in a Shrink Small-Outline Package  
(DBQ)  
•
•
No External Components Required for PLL  
Spread Spectrum Clock Tracking Ability to  
Reduce EMI (SSC)  
DESCRIPTION  
The CDCF5801 provides clock multiplication from a reference clock (REFCLK) signal with the unique capability  
to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3 mUI through a phase aligner. For every rising  
edge on the DLYCTRL pin the CLKOUT is delayed by a 1.3-mUI step size as long as the LEADLAG input  
detects a low signal at the time of the DLYCTRL rising edge. Similarly for every rising edge on the DLYCTRL pin  
the CLKOUT is advanced by a 1.3-mUI step size as long as the LEADLAG pin is high during the transition. This  
unique capability allows the device to phase align (zero delay) between CLKOUT/CLKOUTB and any one other  
CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG pins. Also it  
provides the capability to program a fixed delay by providing the proper number of edges on the DLYCTRL pin,  
while strapping the LEADLAG pin to dc high or low. Further possible applications are:  
•
•
•
•
Aligning the rising edge of the output clock signal to the input clock rising edge  
Avoiding PLL instability in applications that require very long PLL feedback lines  
Isolation of jitter and digital switching noise  
Limitation of jitter in systems with good ppm frequency stability  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2003–2004, Texas Instruments Incorporated  
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中文翻译

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CDCF5801DBQ 替代型号

型号 品牌 替代类型 描述 数据表
CDCF5801DBQR TI

完全替代

 CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
CDCF5801DBQRG4 TI

完全替代

 CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT

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