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CDCFR83ADBQG4 PDF预览

CDCFR83ADBQG4

更新时间: 2024-09-30 11:06:27
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动时钟驱动器时钟发生器
页数 文件大小 规格书
14页 371K
描述
Direct Rambus™ 时钟发生器 | DBQ | 24 | -40 to 85

CDCFR83ADBQG4 数据手册

 浏览型号CDCFR83ADBQG4的Datasheet PDF文件第2页浏览型号CDCFR83ADBQG4的Datasheet PDF文件第3页浏览型号CDCFR83ADBQG4的Datasheet PDF文件第4页浏览型号CDCFR83ADBQG4的Datasheet PDF文件第5页浏览型号CDCFR83ADBQG4的Datasheet PDF文件第6页浏览型号CDCFR83ADBQG4的Datasheet PDF文件第7页 
CDCFR83A  
www.ti.com  
SCAS812AUGUST 2005  
DIRECT RAMBUS™ CLOCK GENERATOR  
FEATURES  
DBQ PACKAGE  
(TOP VIEW)  
533-MHz Differential Clock Source for Direct  
Rambus™ Memory Systems for an 1066-MHz  
Data Transfer Rate  
V
IR  
S0  
S1  
1
24  
DD  
REFCLK  
2
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Fail-Safe Power Up Initialization  
V
P
V
DD  
O
3
DD  
Synchronizes the Clock Domains of the  
Rambus Channel With an External System or  
Processor Clock  
GNDP  
GNDI  
GNDO  
CLK  
4
5
PCLKM  
SYNCLKN  
GNDC  
NC  
6
Three Power Operating Modes to Minimize  
Power for Mobile and Other Power-Sensitive  
Applications  
CLKB  
GNDO  
7
8
V
C
V
DD  
O
9
DD  
Operates From a Single 3.3-V Supply and  
120 mW at 300 MHz (Typ)  
V
DD  
IPD  
MULT0  
MULT1  
S2  
10  
11  
12  
STOPB  
PWRDNB  
Packaged in a Shrink Small-Outline Package  
(DBQ)  
NC − No internal connection  
Supports Frequency Multipliers: 4, 6, 8, 16/3  
No External Components Required for PLL  
Supports Independent Channel Clocking  
Spread Spectrum Clocking Tracking  
Capability to Reduce EMI  
Designed for Use With TI's 133-MHz Clock  
Synthesizers CDC924 and CDC921  
Cycle-Cycle Jitter Is Less Than 40 ps at  
533 MHz  
Certified by Gigatest Labs to Exceed the  
Rambus DRCG Validation Requirement  
Supports Industrial Temperature Range of  
–40°C to 85°C  
DESCRIPTION  
The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus  
memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system or  
processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and mobile  
PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory  
applications.  
The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to enable  
synchronous communication between the Rambus channel and ASIC clock domains. In a Direct Rambus  
memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the DRCG and  
memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK to RDRAMs  
and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK frequencies  
by ratios M and N such that PCLKM = SYNCLKN, where SYNCLK = BUSCLK/4. The DRCG detects the phase  
difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew between  
PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK boundary  
without incurring additional latency.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
DIRECT RAMBUS, Rambus are trademarks of Rambus Inc.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

CDCFR83ADBQG4 替代型号

型号 品牌 替代类型 描述 数据表
CDCFR83ADBQR TI

完全替代

Direct Rambus™ 时钟发生器 | DBQ | 24 | -40 to 85
CDCFR83ADBQ TI

完全替代

Direct Rambus™ 时钟发生器 | DBQ | 24 | -40 to 85

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