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CDCF2510PWLE PDF预览

CDCF2510PWLE

更新时间: 2024-11-16 13:06:43
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器
页数 文件大小 规格书
11页 144K
描述
CDCF SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, PLASTIC, TSSOP-24

CDCF2510PWLE 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:PLASTIC, TSSOP-24针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.33Is Samacsys:N
系列:CDCF输入调节:MUX
JESD-30 代码:R-PDSO-G24长度:7.8 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:24
实输出次数:10最高工作温度:85 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.2 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:OTHER端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mm最小 fmax:140 MHz
Base Number Matches:1

CDCF2510PWLE 数据手册

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CDCF2510  
3.3-V PHASE-LOCK LOOP CLOCK DRIVER  
SCAS628B – APRIL 1999 REVISED NOVEMBER 1999  
PW PACKAGE  
(TOP VIEW)  
Designed to Meet PC133 SDRAM  
Registered DIMM Specification Rev. 0.9  
Spread Spectrum Clock Compatible  
AGND  
CLK  
AV  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
Operating Frequency 25 MHz to 140 MHz  
V
2
CC  
CC  
Static tPhase Error Distribution at 66MHz to  
133 MHz is ±125 ps  
1Y0  
1Y1  
1Y2  
GND  
GND  
1Y3  
V
3
CC  
1Y9  
1Y8  
GND  
GND  
1Y7  
1Y6  
4
5
Jitter (cyc – cyc) at 66 MHz to 133 MHz Is  
|70| ps  
6
7
Available in Plastic 24-Pin TSSOP  
8
Phase-Lock Loop Clock Distribution for  
Synchronous DRAM Applications  
1Y4  
9
V
10  
11  
12  
15 1Y5  
CC  
G
Distributes One Clock Input to One Bank of  
Ten Outputs  
V
14  
13  
CC  
FBOUT  
FBIN  
Output Enable Pin to Enable/Disable All 10  
Outputs  
External Feedback (FBIN) Terminal Is Used  
to Synchronize the Outputs to the Clock  
Input  
On-Chip Series Damping Resistors  
No External RC Network Required  
Operates at 3.3 V  
description  
The CDCF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL  
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.  
It is specifically designed for use with synchronous DRAMs. The CDCF2510 operates at 3.3 V V . It also  
CC  
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.  
One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted  
to 50%, independent of the duty cycle at CLK. The outputs can be enabled/disabled with the control (G) input.  
When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the  
outputs are disabled to the logic-low state.  
Unlike many products containing PLLs, the CDCF2510 does not require external RC networks. The loop filter  
for the PLL is included on-chip, minimizing component count, board space, and cost.  
Because it is based on PLL circuitry, the CDCF2510 requires a stabilization time to achieve phase lock of the  
feedback signal to the reference signal. This stabilization time is required, following power up and application  
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback  
signals. The PLL can be bypassed for test purposes by strapping AV  
to ground.  
CC  
The CDCF2510 is characterized for operation from 0°C to 85°C.  
For application information refer to application reports High Speed Distribution Design Techniques for  
CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread  
Spectrum Clocking (SSC) (literature number SCAA039).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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