CDCF2510PW

更新时间： 2024-09-28 22:40:11

品牌	Logo	应用领域
德州仪器 - TI		时钟驱动器逻辑集成电路光电二极管信息通信管理
页数	文件大小	规格书
11页	144K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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技术参数
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CDCF2510PW 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	TSSOP-24
针数：	24	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	Factory Lead Time：	1 week
风险等级：	5.3	Is Samacsys：	N
系列：	2510	输入调节：	STANDARD
JESD-30 代码：	R-PDSO-G24	JESD-609代码：	e4
长度：	7.8 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.014 A	湿度敏感等级：	1
功能数量：	1	反相输出次数：
端子数量：	24	实输出次数：	10
最高工作温度：	70 °C	最低工作温度：
输出特性：	SERIES-RESISTOR	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP24,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.2 ns
座面最大高度：	1.2 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	BICMOS	温度等级：	COMMERCIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	4.4 mm
最小 fmax：	140 MHz	Base Number Matches：	1

CDCF2510PW 数据手册

CDCF2510

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS628B – APRIL 1999 REVISED NOVEMBER 1999

PW PACKAGE

(TOP VIEW)

Designed to Meet PC133 SDRAM

Registered DIMM Specification Rev. 0.9

Spread Spectrum Clock Compatible

AGND

CLK

Operating Frequency 25 MHz to 140 MHz

Static tPhase Error Distribution at 66MHz to

133 MHz is ±125 ps

1Y0

1Y1

1Y2

GND

1Y3

1Y9

1Y8

GND

1Y7

1Y6

Jitter (cyc – cyc) at 66 MHz to 133 MHz Is

|70| ps

Available in Plastic 24-Pin TSSOP

Phase-Lock Loop Clock Distribution for

Synchronous DRAM Applications

1Y4

15 1Y5

Distributes One Clock Input to One Bank of

Ten Outputs

FBOUT

FBIN

Output Enable Pin to Enable/Disable All 10

Outputs

External Feedback (FBIN) Terminal Is Used

to Synchronize the Outputs to the Clock

Input

On-Chip Series Damping Resistors

No External RC Network Required

Operates at 3.3 V

description

The CDCF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL

to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs. The CDCF2510 operates at 3.3 V V . It also

provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted

to 50%, independent of the duty cycle at CLK. The outputs can be enabled/disabled with the control (G) input.

When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the

outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDCF2510 does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDCF2510 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required, following power up and application

of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback

signals. The PLL can be bypassed for test purposes by strapping AV

to ground.

The CDCF2510 is characterized for operation from 0°C to 85°C.

For application information refer to application reports High Speed Distribution Design Techniques for

CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread

Spectrum Clocking (SSC) (literature number SCAA039).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...11

中文翻译

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CDCF2510PW 替代型号

型号	品牌	替代类型	描述	数据表
CDCVF2510PWR	TI	类似代替	适用于 DRAM 应用且具有 10 个输出的 3.3V 锁相环路时钟驱动器 \| PW \|
CDCVF2510APW	TI	类似代替	3.3-V Phase-Lock Loop Clock Driver with Power Down Mode 24-TSSOP 0 to 85
CDCVF2510PW	TI	类似代替	3.3-V PHASE-LOCK LOOP CLOCK DRIVER

与CDCF2510PW相关器件

型号	品牌	获取价格	描述	数据表
CDCF2510PWLE	TI	获取价格	CDCF SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, PLAS
CDCF2510PWR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCF5801	TI	获取价格	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
CDCF5801_14	TI	获取价格	CLOCK MULTIPLIER
CDCF5801A	TI	获取价格	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
CDCF5801ADBQ	TI	获取价格	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
CDCF5801ADBQG4	TI	获取价格	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
CDCF5801ADBQR	TI	获取价格	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
CDCF5801ADBQRG4	TI	获取价格	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
CDCF5801DBQ	TI	获取价格	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT

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