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74V1T79 PDF预览

74V1T79

更新时间: 2024-11-03 22:45:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器
页数 文件大小 规格书
9页 116K
描述
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP

74V1T79 数据手册

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74V1T79  
SINGLE POSITIVE EDGE TRIGGERED  
D-TYPE FLIP-FLOP  
HIGH SPEED:  
f
t
= 180MHz (TYP.) at V = 5V  
MAX  
CC  
= 3.9ns (TYP.) at V = 5V  
CK-Q  
CC  
LOW POWER DISSIPATION:  
= 1µA(MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS:  
= 2V (MIN), V = 0.8V (MAX)  
V
SOT23-5L  
SOT323-5L  
T & R  
IH  
IL  
POWER DOWN PROTECTION ON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8mA (MIN) at V = 4.5V  
ORDER CODES  
OH  
OL  
CC  
BALANCED PROPAGATION DELAYS:  
PACKAGE  
t
t
PLH  
PHL  
SOT23-5L  
74V1T79STR  
74V1T79CTR  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
SOT323-5L  
V
CC  
IMPROVED LATCH-UP IMMUNITY  
Following the hold time interval, data at the D input  
can be changed without affecting the level at the  
output. Power down protection is provided on  
inputs and 0 to 7V can be accepted on inputs with  
no regard to the supply voltage. This device can  
be used to interface 5V to 3V systems.  
DESCRIPTION  
The 74V1T79 is an advanced high-speed CMOS  
SINGLE POSITIVE EDGE TRIGGERED D-TYPE  
FLIP-FLOP fabricated with sub-micron silicon  
2
gate and double-layer metal wiring C MOS  
technology. It is designed to operate from 4.5V to  
5.5V, making this device ideal for portable  
applications.  
This D-Type flip-flop is controlled by a clock input  
(CK). On the positive transition of the clock, the Q  
output will be set to the logic state that was setup  
at the D input.  
It’s available in the commercial and extended  
temperature range.  
All inputs and output are equipped with protection  
circuits against static discharge, giving them ESD  
immunity and transient excess voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2004  
1/9  

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