Datasheet > 74V1T70CTR

74V1T70CTR

更新时间： 2024-09-28 23:24:35

品牌	Logo	应用领域
其他 - ETC		触发器逻辑集成电路光电二极管栅
页数	文件大小	规格书
9页	65K
描述
LOGIC GATE\|BUFFER\|CMOS\|TSSOP\|6PIN\|PLASTIC

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中文翻译

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数据手册

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74V1T70CTR 数据手册

74V1T70

SINGLE BUFFER

■

HIGH SPEED: t =3.6ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 1µA(MAX.) at T =25°C

■

COMPATIBLE WITH TTL OUTPUTS:

= 2V (MIN), V = 0.8V (MAX)

■

POWER DOWN PROTECTION ON INPUT

SYMMETRICAL OUTPUT IMPEDANCE:

SOT23-5L

SOT323-5L

T & R

|I | = I = 8mA (MIN) at V = 4.5V

■

BALANCED PROPAGATION DELAYS:

ORDER CODES

PLH

PHL

OPERATING VOLTAGE RANGE:

(OPR) = 4.5V to 5.5V

PACKAGE

SOT23-5L

74V1T70STR

74V1T70CTR

IMPROVED LATCH-UP IMMUNITY

SOT323-5L

DESCRIPTION

Power down protection is provided on input and 0

to 7V can be accepted on input with no regard to

the supply voltage. This device can be used to

interface 5V to 3V.

The 74V1T70 is an advanced high-speed CMOS

SINGLE BUFFER fabricated with sub-micron

silicon gate and double-layer metal wiring C MOS

technology.

The internal circuit is composed of 2 stages

including buffer output, which provide high noise

immunity and stable output.

PIN CONNECTION AND IEC LOGIC SYMBOLS

July 2001

1/9

12 3 4 5 6 7...9

中文翻译

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