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74V1T77 PDF预览

74V1T77

更新时间: 2024-11-03 21:53:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 锁存器
页数 文件大小 规格书
10页 211K
描述
SINGLE D-TYPE LATCH

74V1T77 数据手册

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74V1T77  
SINGLE D-TYPE LATCH  
HIGH SPEED: t = 4.7ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 1µA(MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS:  
= 2V (MIN), V = 0.8V (MAX)  
V
IH  
IL  
POWER DOWN PROTECTION ON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
SOT23-5L  
SOT323-5L  
T & R  
|I | = I = 8mA (MIN) at V = 4.5V  
OH  
OL  
CC  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
t
t
PLH  
PHL  
PACKAGE  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
SOT23-5L  
74V1T77STR  
74V1T77CTR  
V
CC  
SOT323-5L  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
output is latched precisely at the logic level of D  
data input.  
Power down protection is provided on inputs and  
0 to 7V can be accepted on inputs with no regard  
to the supply voltage. This device can be used to  
interface 5V to 3V.  
It’s available in the commercial and extended  
temperature range.  
All inputs and output are equipped with protection  
circuits against static discharge, giving them ESD  
immunity and transient excess voltage.  
The 74V1T77 is an advanced high-speed CMOS  
SINGLE D-TYPE LATCH fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS technology. It is designed to  
operate from 4.5V to 5.5V, making this device  
ideal for portable applications.  
The single D-Type latch is controlled by an Latch  
Enable Input (LE). While the LE input is held at a  
high level, the Q output will follow the data input  
precisely. When the LE input is taken low the Q  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/10  

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