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VNS1NV04D13TR PDF预览

VNS1NV04D13TR

更新时间: 2024-11-12 23:45:11
品牌 Logo 应用领域
其他 - ETC 晶体接口集成电路晶体管光电二极管驱动
页数 文件大小 规格书
14页 158K
描述
TRANSISTOR | MOSFET | MATCHED PAIR | N-CHANNEL | SO

VNS1NV04D13TR 数据手册

 浏览型号VNS1NV04D13TR的Datasheet PDF文件第2页浏览型号VNS1NV04D13TR的Datasheet PDF文件第3页浏览型号VNS1NV04D13TR的Datasheet PDF文件第4页浏览型号VNS1NV04D13TR的Datasheet PDF文件第5页浏览型号VNS1NV04D13TR的Datasheet PDF文件第6页浏览型号VNS1NV04D13TR的Datasheet PDF文件第7页 
VNS1NV04D  
“OMNIFET II”:  
FULLY AUTOPROTECTED POWER MOSFET  
TYPE  
RDS(on)  
Ilim  
Vclamp  
VNS1NV04D 250 m(*)  
1.7 A (*)  
40 V (*)  
(*) Per each device  
n LINEAR CURRENT LIMITATION  
n THERMAL SHUT DOWN  
n SHORT CIRCUIT PROTECTION  
n INTEGRATED CLAMP  
n LOW CURRENT DRAWN FROM INPUT PIN  
n DIAGNOSTIC FEEDBACK THROUGH INPUT  
PIN  
SO-8  
n ESD PROTECTION  
n DIRECT ACCESS TO THE GATE OF THE  
POWER MOSFET (ANALOG DRIVING)  
n COMPATIBLE WITH STANDARD POWER  
MOSFET  
Technology: they are intended for replacement of  
standard Power MOSFETS from DC up to 50KHz  
applications. Built in thermal shutdown, linear  
current limitation and overvoltage clamp protects  
the chip in harsh environments.  
DESCRIPTION  
The VNS1NV04D is a device formed by two  
monolithic OMNIFET II chips housed in  
a
standard SO-8 package. The OMNIFET II are  
designed in STMicroelectronics VIPower M0-3  
Fault feedback can be detected by monitoring the  
voltage at the input pin.  
BLOCK DIAGRAM  
DRAIN1  
DRAIN2  
OVERVOLTAGE  
CLAMP  
OVERVOLTAGE  
CLAMP  
INPUT2  
GATE  
CONTROL  
INPUT1  
GATE  
CONTROL  
LINEAR  
LINEAR  
CURRENT  
CURRENT  
OVER  
OVER  
LIMITER  
LIMITER  
TEMPERATURE  
TEMPERATURE  
SOURCE1  
SOURCE2  
March 2002  
1/14  
1

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