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UPA2721AGR-E1-AT PDF预览

UPA2721AGR-E1-AT

更新时间: 2024-11-06 21:18:15
品牌 Logo 应用领域
日电电子 - NEC 开关脉冲光电二极管晶体管
页数 文件大小 规格书
6页 160K
描述
Power Field-Effect Transistor, 19A I(D), 30V, 0.01ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, ROHS COMPLIANT, POWER, SOP-8

UPA2721AGR-E1-AT 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SOT包装说明:SMALL OUTLINE, R-PDSO-G8
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99风险等级:5.3
雪崩能效等级(Eas):36 mJ配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:30 V最大漏极电流 (ID):19 A
最大漏源导通电阻:0.01 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
元件数量:1端子数量:8
工作模式:ENHANCEMENT MODE封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED极性/信道类型:N-CHANNEL
最大脉冲漏极电流 (IDM):200 A认证状态:Not Qualified
表面贴装:YES端子面层:MATTE TIN
端子形式:GULL WING端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

UPA2721AGR-E1-AT 数据手册

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DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
μPA2721AGR  
SWITCHING  
N-CHANNEL POWER MOS FET  
DESCRIPTION  
PACKAGE DRAWING (Unit: mm)  
The μ PA2721AGR is N-channel MOS Field Effect Transistor  
designed for power management applications of a notebook  
computer.  
8
5
1, 2, ꢀ : Source  
4
: Gate  
5, 6, 7, 8: Drain  
FEATURES  
Low on-state resistance  
RDS(on)1 = 4.3 mΩ MAX. (VGS = 10 V, ID = 10 A)  
RDS(on)2 = 10 mΩ MAX. (VGS = 5.0 V, ID = 10 A)  
Low input capacitance  
6.0 0.ꢀ  
4.4  
1
4
5.ꢀ7 MAX.  
0.8  
Ciss = 7100 pF TYP. (VDS = 10 V, VGS = 0 V)  
Built-in gate protection diode  
Small and surface mount package (Power SOP8)  
RoHS Compliant  
0.5 0.2  
0.10  
1.27 0.78 MAX.  
+0.10  
0.40  
0.12 M  
–0.05  
ORDERING INFORMATION  
PART NUMBER  
LEAD PLATING  
Pure Sn  
PACKING  
PACKAGE  
μ PA2721AGR-E1-AT Note  
μ PA2721AGR-E2-AT Note  
Power SOP8  
0.08 g TYP.  
Tape 2500 p/reel  
Note Pb-free (This product does not contain Pb in external electrode and other parts.)  
EQUIVALENT CIRCUIT  
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)  
Drain to Source Voltage (VGS = 0 V)  
Gate to Source Voltage (VDS = 0 V)  
Drain Current (DC)  
VDSS  
VGSS  
ID(DC)  
ID(pulse)  
PT1  
30  
V
V
Drain  
20  
19  
200  
A
Drain Current (pulse) Note1  
Body  
Diode  
A
Gate  
Total Power Dissipation Note2  
Total Power Dissipation (PW = 10 sec) Note2  
Channel Temperature  
1.1  
W
W
°C  
°C  
A
PT2  
2.5  
Gate  
Protection  
Diode  
Tch  
150  
Source  
Storage Temperature  
Tstg  
55 to +150  
19  
Single Avalanche Current Note3  
Single Avalanche Energy Note3  
Notes 1. PW 10 μs, Duty Cycle 1%  
IAS  
EAS  
36  
mJ  
2. Mounted on glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mmt  
3. Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, VGS = 20 0 V, L = 100 μH  
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When  
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated  
voltage may be applied to this device.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. G18705EJ1V0DS00 (1st edition)  
Date Published September 2008 NS  
Printed in Japan  
2007, 2008  

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