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UPA2728GR-E1-A PDF预览

UPA2728GR-E1-A

更新时间: 2024-09-16 21:10:27
品牌 Logo 应用领域
日电电子 - NEC ISM频段开关脉冲光电二极管晶体管
页数 文件大小 规格书
6页 163K
描述
Power Field-Effect Transistor, 13A I(D), 30V, 0.018ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, POWER SOP-8

UPA2728GR-E1-A 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:POWER SOP-8Reach Compliance Code:compliant
风险等级:5.68雪崩能效等级(Eas):17 mJ
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:30 V
最大漏极电流 (ID):13 A最大漏源导通电阻:0.018 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-PDSO-G8
JESD-609代码:e3/e6元件数量:1
端子数量:8工作模式:ENHANCEMENT MODE
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
极性/信道类型:N-CHANNEL最大脉冲漏极电流 (IDM):52 A
认证状态:Not Qualified表面贴装:YES
端子面层:MATTE TIN/TIN BISMUTH端子形式:GULL WING
端子位置:DUAL处于峰值回流温度下的最长时间:10
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

UPA2728GR-E1-A 数据手册

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DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
μPA2728GR  
SWITCHING  
N-CHANNEL POWER MOS FET  
PACKAGE DRAWING (Unit: mm)  
DESCRIPTION  
The μ PA2728GR is N-channel MOS Field Effect Transistor  
designed for DC/DC converter and power management  
applications of notebook computer.  
8
5
1, 2, 3 : Source  
4
: Gate  
5, 6, 7, 8: Drain  
FEATURES  
Low on-state resistance  
RDS(on)1 = 10.5 mΩ MAX. (VGS = 10 V, ID = 7.0 A)  
RDS(on)2 = 18 mΩ MAX. (VGS = 4.5 V, ID = 7.0 A)  
Low gate to drain charge  
6.0 ±0.3  
4.4  
1
4
5.37 MAX.  
0.8  
QGD = 3.5 nC TYP. (VDD = 15 V, ID = 13 A)  
Built-in gate protection diode  
Small and surface mount package (Power SOP8)  
RoHS Compliant  
0.5 ±0.2  
0.10  
1.27 0.78 MAX.  
+0.10  
0.40  
0.12 M  
–0.05  
ORDERING INFORMATION  
PART NUMBER  
LEAD PLATING  
Sn-Bi  
PACKING  
PACKAGE  
μ PA2728GR-E1-A Note  
μ PA2728GR-E2-A Note  
μ PA2728GR-E1-AT Note  
μ PA2728GR-E2-AT Note  
Power SOP8  
0.08 g TYP.  
Tape 2500 p/reel  
Pure Sn  
Note Pb-free (This product does not contain Pb in external electrode and other parts).  
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)  
EQUIVALENT CIRCUIT  
Drain to Source Voltage (VGS = 0 V)  
Gate to Source Voltage (VDS = 0 V)  
Drain Current (DC)  
VDSS  
VGSS  
ID(DC)  
ID(pulse)  
PT1  
30  
V
V
Drain  
25  
13  
A
Drain Current (pulse) Note1  
Body  
Diode  
52  
A
Gate  
Total Power Dissipation Note2  
Total Power Dissipation (PW = 10 sec) Note2  
Channel Temperature  
1.1  
W
W
°C  
°C  
A
PT2  
2.5  
150  
Gate  
Protection  
Diode  
Tch  
Source  
Storage Temperature  
Tstg  
55 to +150  
13  
Single Avalanche Current Note3  
Single Avalanche Energy Note3  
IAS  
EAS  
17  
mJ  
Notes 1. PW 10 μs, Duty Cycle 1%  
2. Mounted on glass epoxy board of 1 inch2 x 0.8 mm  
3. Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, VGS = 20 0 V, L = 100 μH  
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When  
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated  
voltage may be applied to this device.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. G18295EJ1V0DS00 (1st edition)  
Date Published March 2007 NS CP(K)  
Printed in Japan  
2006, 2007  

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