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UPA2730TP

更新时间： 2024-11-05 22:35:43
品牌 Logo 应用领域
日电电子 - NEC 晶体小信号场效应晶体管开关光电二极管
页数 文件大小 规格书
8页 82K
描述
SWITCHING P-CHANNEL POWER MOSFET

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中文翻译

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UPA2730TP 技术参数

是否Rohs认证：不符合生命周期：Transferred
包装说明：POWER, HSOP-8Reach Compliance Code：compliant
风险等级：5.77Is Samacsys：N
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：30 V
最大漏极电流 (ID)：42 A最大漏源导通电阻：0.012 Ω
FET 技术：METAL-OXIDE SEMICONDUCTOR最大反馈电容 (Crss)：760 pF
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
元件数量：1端子数量：8
工作模式：ENHANCEMENT MODE封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED极性/信道类型：P-CHANNEL
认证状态：Not Qualified表面贴装：YES
端子面层：TIN LEAD端子形式：GULL WING
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

UPA2730TP 数据手册

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DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
µPA2730TP  
SWITCHING  
P-CHANNEL POWER MOS FET  
DESCRIPTION  
PACKAGE DRAWING (Unit: mm)  
The µPA2730TP which has a heat spreader is P-Channel  
MOS Field Effect Transistor designed for power management  
applications of notebook computers and Li-ion battery  
protection circuit.  
8
5
1, 2, 3  
4
5, 6, 7, 8, 9 ; Drain  
; Source  
; Gate  
FEATURES  
• Low on-state resistance  
6.0 ±0.3  
1
4
0.8 ±0.2  
4.4 ±0.15  
+0.17  
–0.2  
5.2  
RDS(on)1 = 7.0 mΩ MAX. (VGS = –10 V, ID = –7.5 A)  
RDS(on)2 = 10.5 mΩ MAX. (VGS = –4.5 V, ID = –7.5 A)  
RDS(on)3 = 12.0 mΩ MAX. (VGS = –4.0 V, ID = –7.5 A)  
• Low Ciss: Ciss = 4670 pF TYP.  
S
0.10  
S
1.27 TYP.  
+0.10  
–0.05  
0.40  
0.12 M  
• Small and surface mount package (Power HSOP8)  
1
4
2.0 ±0.2  
9
ORDERING INFORMATION  
4.1 MAX.  
PART NUMBER  
PACKAGE  
µPA2730TP  
Power HSOP8  
8
5
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, Unless otherwise noted, All terminals are connected.)  
Drain to Source Voltage (VGS = 0 V)  
Gate to Source Voltage (VDS = 0 V)  
Drain Current (DC) (TC = 25°C)  
Drain Current (DC) Note1  
VDSS  
VGSS  
ID(DC)1  
ID(DC)2  
ID(pulse)  
PT1  
−30  
V
V
m20  
m42  
m20  
m120  
40  
A
EQUIVALENT CIRCUIT  
A
Drain Current (pulse) Note2  
Drain  
A
Total Power Dissipation (TC = 25°C)  
Total Power Dissipation (TA = 25°C) Note1  
Channel Temperature  
W
W
°C  
°C  
A
PT2  
3
Body  
Tch  
150  
Diode  
Gate  
Storage Temperature  
Tstg  
−55 to + 150  
−15  
Single Avalanche Current Note3  
Single Avalanche Energy Note3  
IAS  
EAS  
22.5  
mJ  
Source  
Notes 1. Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm), PW = 10 sec  
2. PW ≤ 10 µs, Duty Cycle ≤ 1%  
3. Starting Tch = 25°C, VDD = –15 V, RG = 25 Ω, L = 100 µH, VGS = –20 → 0 V  
Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately  
degrade the device operation. Steps must be taken to stop generation of static electricity as much as  
possible, and quickly dissipate it once, when it has occurred.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with NEC Electronics sales  
representative for availability and additional information.  
Document No.  
G15983EJ1V0DS00 (1st edition)  
Date Published November 2002 NS CP(K)  
Printed in Japan  
2002  
12345678

中文翻译

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