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SY100E131JC PDF预览

SY100E131JC

更新时间: 2024-11-23 20:31:47
品牌 Logo 应用领域
美国微芯 - MICROCHIP 逻辑集成电路触发器
页数 文件大小 规格书
5页 99K
描述
D Flip-Flop, 100E Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, ECL, PQCC28

SY100E131JC 技术参数

生命周期:Active包装说明:QCCJ, LDCC28,.5SQ
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.16其他特性:LVECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.5V
系列:100EJESD-30 代码:S-PQCC-J28
长度:11.48 mm逻辑集成电路类型:D FLIP-FLOP
位数:4功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
最大电源电流(ICC):81 mA传播延迟(tpd):0.675 ns
座面最大高度:4.57 mm表面贴装:YES
技术:ECL温度等级:OTHER
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD触发器类型:POSITIVE EDGE
宽度:11.48 mm最小 fmax:1100 MHz
Base Number Matches:1

SY100E131JC 数据手册

 浏览型号SY100E131JC的Datasheet PDF文件第2页浏览型号SY100E131JC的Datasheet PDF文件第3页浏览型号SY100E131JC的Datasheet PDF文件第4页浏览型号SY100E131JC的Datasheet PDF文件第5页 
NOT RECOMMENDED FOR NEW DESIGNS  
4-BIT D  
SY10E131  
SY100E131  
FLIP-FLOP  
DESCRIPTION  
FEATURES  
1100MHz min. toggle frequency  
Extended 100E VEE range of –4.2V to –5.5V  
Differential output  
The SY10/100E131 are high-speed quad master slave  
D-type flip-flops with differential outputs designed for use  
in new, high-performance ECL systems. The flip-flops may  
be individually clocked by holding CC (Common Clock) at  
a logic LOW and then using the four individual CE (Clock  
Enable CE0–CE3) inputs to accomplish such clocking.  
Alternatively, all four flip-flops can be clocked in common  
by holding the CE inputs LOW and then using CC to clock  
the data. In the common clock mode, the CE input acts as  
a control that passes the CC signal to the flip-flop. Data is  
clocked into the flip-flop on the rising edge of the output of  
the logical OR operation between CE and CC (data enters  
the master when both CC and CE are LOW and data  
transfers to the slave when either CE or CC, or both, go  
HIGH).  
Individual and common clocks  
Indivldual asynchronous reset  
Paired asynchronous sets  
Fully compatible with Industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E131  
Available in 28-pin PLCC package  
Asynchronous set and reset controls are provided. The  
reset controls are individual and the set controls are  
pairwise.  
PIN NAMES  
Pin  
Function  
Data Inputs  
D0-D3  
CE0-CE3  
R0-R3  
CC  
Clock Enables (Individual)  
Resets  
Common Clock  
Sets (paired)  
S03, S12  
Q0-Q3  
Q0-Q3  
VCCO  
True Outputs  
Inverting Outputs  
VCC to Output  
Rev.: H  
Amendment: /0  
M9999-032006  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

SY100E131JC 替代型号

型号 品牌 替代类型 描述 数据表
MC100E131FNR2 ONSEMI

类似代替

5V ECL 4-Bit D Flip-Flop

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