SY100E136

更新时间： 2024-11-25 22:42:35

品牌	Logo	应用领域
麦瑞 - MICREL		计数器
页数	文件大小	规格书
8页	122K
描述
6-BIT UNIVERSAL UP/DOWN COUNTER

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中文翻译

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数据手册

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SY100E136 数据手册

6-BIT UNIVERSAL

SY10E136

UP/DOWN COUNTER

SY100E136

DESCRIPTION

FEATURES

■ 550MHz count frequency

The SY10/100E136 are 6-bit synchronous, presettable,

cascadable universal counters. These devices generate

a look-ahead-carry output and accept a look-ahead-carry

input. These two features allow for the cascading of

multiple E136s for wider bit width counters that operate

at very nearly the same frequency as the stand-alone

counter.

The CLOUT output will pulse LOW for one clock cycle

one count before the E136 reaches terminal count. The

COUT output will pulse LOW for one clock cycle when

the counter reaches terminal count. For more information

on utilizing the look-ahead-carry features of the device,

please refer to the applications section of this data sheet.

The differential COUT output facilitates the E136's use in

programmable divider and self-stopping counter

applications.

■ Extended 100E VEE range of –4.2V to –5.5V

■ Look-ahead-carry input and output

■ Fully synchronous up and down counting

■ Asynchronous Master Reset

■ Internal 75KΩ input pull-down resistors

■ Available in 28-pin PLCC package

PIN CONFIGURATION

Unlike the H136 and other similar universal counter

designs, the E136 carry-out and look-ahead-carry-out

signals are registered on chip. This design alleviates the

glitch problem seen on many counters where the carry-

out signals are merely gated. Because of this architecture,

there are some minor functional differences between the

E136 and H136 counters. The user, regardless of

familiarity with the H136, should read this data sheet

carefully. Note specifically (see block diagram) the

operation of the carry-out outputs and the look-ahead-

carry-in input when utilizing the Master Reset.

25 24 23 22 21 20 19

VCC

PLCC

TOP VIEW

J28-1

VEE

VCCO

COUT

CLK

CIN

CLIN

CLOUT

10 11

When left open, all of the input pins will be pulled

LOW via an input pulldown resistor. The Master Reset is

an asynchronous signal which, when asserted, will force

the Q outputs LOW.

The Q outputs need not be terminated for the E136 to

function properly. In fact, if these outputs will not be

used in a system, it is recommended that they be left

open to save power and minimize noise. This practice

will minimize switching noise which can reduce the

maximum count frequency of the device, or significantly

reduce margins against other noise in the system.

PIN NAMES

D0–D5

Q0–Q5

S1, S2

Function

Preset Data Inputs

Differential Data Outputs

Mode Control Pins

Master Reset

CLK

Clock Input

COUT, COUT

CLOUT

CIN

Carry Out Output (Active LOW)

Look-Ahead-Carry Output

Carry-In Input (Active LOW)

Look-Ahead-Carry Input

VCC to Output

CLIN

VCCO

Rev.: C

Amendment:/1

Issue Date: February, 1998

12 3 4 5 6 7 8

中文翻译

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与SY100E136相关器件

型号	品牌	获取价格	描述	数据表
SY100E136JC	MICREL	获取价格	6-BIT UNIVERSAL UP/DOWN COUNTER
SY100E136JCTR	MICREL	获取价格	6-BIT UNIVERSAL UP/DOWN COUNTER
SY100E136JZ	MICREL	获取价格	6-BIT UNIVERSAL UP/DOWN COUNTER
SY100E136JZTR	MICREL	获取价格	6-BIT UNIVERSAL UP/DOWN COUNTER
SY100E137	MICREL	获取价格	8-BIT RIPPLE COUNTER
SY100E137JC	MICREL	获取价格	8-BIT RIPPLE COUNTER
SY100E137JCTR	MICREL	获取价格	8-BIT RIPPLE COUNTER
SY100E137JZ	MICREL	获取价格	8-BIT RIPPLE COUNTER
SY100E137JZTR	MICREL	获取价格	8-BIT RIPPLE COUNTER
SY100E141	MICREL	获取价格	8-BIT SHIFT REGISTER

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