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SY100E136JZ PDF预览

SY100E136JZ

更新时间: 2024-01-24 18:31:06
品牌 Logo 应用领域
麦瑞 - MICREL 计数器触发器逻辑集成电路
页数 文件大小 规格书
9页 98K
描述
6-BIT UNIVERSAL UP/DOWN COUNTER

SY100E136JZ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCJ, LDCC28,.5SQ针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.54计数方向:BIDIRECTIONAL
系列:100EJESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.48 mm
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:550000000 Hz工作模式:SYNCHRONOUS
湿度敏感等级:2位数:6
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:-4.5 V
最大电源电流(ICC):170 mA传播延迟(tpd):1.45 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Counters表面贴装:YES
技术:ECL温度等级:OTHER
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40触发器类型:POSITIVE EDGE
宽度:11.48 mm最小 fmax:550 MHz
Base Number Matches:1

SY100E136JZ 数据手册

 浏览型号SY100E136JZ的Datasheet PDF文件第2页浏览型号SY100E136JZ的Datasheet PDF文件第3页浏览型号SY100E136JZ的Datasheet PDF文件第4页浏览型号SY100E136JZ的Datasheet PDF文件第5页浏览型号SY100E136JZ的Datasheet PDF文件第6页浏览型号SY100E136JZ的Datasheet PDF文件第7页 
6  
6-BIT UNIVERSAL  
SY10E136  
SY100E136  
UP/DOWN COUNTER  
DESCRIPTION  
FEATURES  
550MHz count frequency  
The SY10/100E136 are 6-bit synchronous, presettable,  
cascadable universal counters. These devices generate  
a look-ahead-carry output and accept a look-ahead-carry  
input. These two features allow for the cascading of  
multiple E136s for wider bit width counters that operate  
at very nearly the same frequency as the stand-alone  
counter.  
The CLOUT output will pulse LOW for one clock cycle  
one count before the E136 reaches terminal count. The  
COUT output will pulse LOW for one clock cycle when  
the counter reaches terminal count. For more information  
on utilizing the look-ahead-carry features of the device,  
please refer to the applications section of this data sheet.  
The differential COUT output facilitates the E136's use in  
programmable divider and self-stopping counter  
applications.  
Unlike the H136 and other similar universal counter  
designs, the E136 carry-out and look-ahead-carry-out  
signals are registered on chip. This design alleviates the  
glitch problem seen on many counters where the carry-  
out signals are merely gated. Because of this architecture,  
there are some minor functional differences between the  
E136 and H136 counters. The user, regardless of  
familiarity with the H136, should read this data sheet  
carefully. Note specifically (see block diagram) the  
operation of the carry-out outputs and the look-ahead-  
carry-in input when utilizing the Master Reset.  
Extended 100E VEE range of –4.2V to –5.5V  
Look-ahead-carry input and output  
Fully synchronous up and down counting  
Asynchronous Master Reset  
Internal 75Kinput pull-down resistors  
Available in 28-pin PLCC package  
PIN NAMES  
Pin  
D0–D5  
Function  
Preset Data Inputs  
Q0–Q5  
S1, S2  
MR  
Differential Data Outputs  
Mode Control Pins  
Master Reset  
CLK  
Clock Input  
COUT, COUT  
CLOUT  
CIN  
Carry Out Output (Active LOW)  
Look-Ahead-Carry Output  
Carry-In Input (Active LOW)  
Look-Ahead-Carry Input  
VCC to Output  
When left open, all of the input pins will be pulled  
LOW via an input pulldown resistor. The Master Reset is  
an asynchronous signal which, when asserted, will force  
the Q outputs LOW.  
CLIN  
VCCO  
The Q outputs need not be terminated for the E136 to  
function properly. In fact, if these outputs will not be  
used in a system, it is recommended that they be left  
open to save power and minimize noise. This practice  
will minimize switching noise which can reduce the  
maximum count frequency of the device, or significantly  
reduce margins against other noise in the system.  
Rev.: F  
Amendment: 0  
M9999-032006  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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