Datasheet > SY100E150JCTR

SY100E150JCTR

更新时间： 2024-11-18 22:42:35

品牌	Logo	应用领域
麦瑞 - MICREL		触发器逻辑集成电路
页数	文件大小	规格书
4页	63K
描述
6-BIT D LATCH

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中文翻译

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数据手册

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SY100E150JCTR 数据手册

6-BIT D

LATCH

SY10E150

SY100E150

DESCRIPTION

FEATURES

■ 700ps max. propagation delay

■ Extended 100E VEE range of –4.2V to –5.5V

■ Differential outputs

The SY10/100E150 are 6-bit D latches with differential

outputs designed for use in new, high- performance ECL

systems. When both Latch Enables (LEN1, LEN2) are at a

logic LOW, the latch is in the transparent mode and input

data propagates through to the output. A logic HIGH on

either LEN1 or LEN2 (or both) latches the input data. The

Master Reset (MR) overrides all other signals to set the Q

outputs to a logic LOW.

■ Fully compatible with industry standard 10KH,

100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E150

■ Available in 28-pin PLCC package

BLOCK DIAGRAM

PIN CONFIGURATION

24 23 22 21 20 19

PLCC

TOP VIEW

J28-1

VEE

10 11

LEN

PIN NAMES

D0–D5

LEN1, LEN2

Function

Data Inputs

Latch Enables

Master Reset

True Outputs

Q0–Q5

VCCO

Inverting Outputs

VCC to Output

Rev.: D

Amendment: /0

Issue Date: November, 1998

12 3 4

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